Application of the polysilicon edge sealed LOCOS process in scaled VLSI circuit fabrication

Application of the polysilicon edge sealed LOCOS process in scaled VLSI circuit fabrication

Application of the polysilicon edge sealed LOCOS process in scaled VLSI circuit fabrication D. Simeonov, T. Balabanska, E, Goranova, M. Zvetkova, T. D...

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Application of the polysilicon edge sealed LOCOS process in scaled VLSI circuit fabrication D. Simeonov, T. Balabanska, E, Goranova, M. Zvetkova, T. Dimitrova and Z. Naidenova Institute of Microelectronics, Sofia, Bulgaria A polysilicon sealed pad oxide local oxidation process has been investigated. The oxidation mask in this method has a polysilicon frame formed along the perimeter of a conventional mask pattern by a self-aligned technique. This technology is completely free of "bird's beak" formation which is particularly important for increasing the packing density. 1. Introduction The field isolation of a device on a silicon substrate is one of the most important process steps in the fabrication of integrated circuits. Local oxidation has been the standard isolation technology for MOS ICs for about 10 years [1]. The basic problem with LOCOS isolation for future VLSI fabrication is wasted space due to lateral oxidation under the nitride mask. A much improved version based on framing the edges to reduce lateral oxidation has been developed [2]. In comparison with LOCOS this method is quite complicated. This leads to a considerable increase of the production cost and thus restricts their practical application. 2. Polysilicon edge sealed LOCOS process The main results of an experimental investigation of a new isolation teChnique, suggested by Marsten et el. [3], are presented in this paper. The technological sequence is illustrated in Fig. 1. In comparison with the standard LOCOS process only three technological steps were added - thin oxide etching, polysilicon deposition and directional polysilicon etching. This is one of the simplest possible solutions for isolation of VLSI ICs. In our opinion this method will be of practical interest if the device electrical characteristics and the quality of isolation meet the requirements of IC fabrication. The basic idea of the technique is to avoid the oxidant species diffusing under the nitride mask by using sidewall masking of the initial oxide with polysilicon. For this process the notation SOLO (Sealed pad Oxide Local Oxidation) will be used. It turned out that the layer thicknesses and technological process parameters can be chosen in such a way that the field oxide penetration under the nitride mask is eliminated. It is clear that for this process it is necessary that the polysilicon spacers be sufficiently large. In our case this has been achieved by RIE in SF6 plasma. The process duration was estimated in such a way that the calculated thickness of the layer after the etching was in the range 50 - 250 A ~ In Figs. 2 and 3 cross-section views are shown of active regions after the growth of the sacrificial oxide realised by SOLO and LOCOS processes respectively. From Fig. 2 it is clearly seen that SOLO preserves the dimensions defined by the plasma etching of the silicon nitride layer. The characteristic oxide frame on the outside contour of the active regions is a result of the spacer oxidation. Its height can be reduced considerably by a suitable choice of the isotropic etching after the field oxidation and the removal of the sacrificial oxide but its complete elimination is only possible if a definite planarization procedure is used. The

MICROELECTRONICS JOURNAL VoL 19 No. 5 9 1988 Elsevier Science Publishers Ltd., England

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Fig. 1 PolysUieon edge sealed LOCOS process sequence introduction of additional Operations for planarization would make the isolation technique as complicated as some of those already investigated [4]. In order to preserve our main advantage (the simplicity), in our experiments no additional planarization was done. In order to study the isolation quality and the device characteristics using a conventional NMOS process (HMOS II design rules) an experimental test chip was fabricated. The high temperature treatments were performed at 900~ with exception of the PSG reflow which was done at 1000~ The gate oxide thickness is 400 A ~ The ion implantation parameters are presented in Table 1.

12

Fig. 2 Cross-section view of active region after the growth of the sacrificial oxide, realised by the SOLO process

Fig. 3 Cross-section view of active region after the growth of the sacrificial oxide, realised by the LOCOS process 13

TABLE I Ion implantation parameters CHANNEL STOP

B

80 KeV

6.5

ENHANCEMENT MOST

B

35 KeV 160 KeV

5 • 1011 cm -2 4 • 1011 cm -2

DEPLETION MOST

As

120 KeV

1.2 • 1012 cm -2

SOURCE/DRAIN

As

100 KeV

1 • 10le cm -2

X

101/'cm 2

3. Results and discussion The applicability of the SOLO isolation for MOS ICs is examined by test device characteristics. Electrical parameters associated with isolation quality are: junction-junction breakdown voltage (or close diffusion line breakdown voltage); 9 threshold and breakdown voltages of field oxide transistors; 9 gate oxide failure in the oxide region along the field oxide edge. 9

Fig. 4 shows the dependence of close diffusion line breakdown voltage at 1• 10:8 Avs. the mask distance between them for two doses of the field implantation. It is seen that.when the field implantation dose is greater than or equal to 4• 1012 cm -2 a distance of 1.51amguarantees a breakdown voltage higher than 10 V. Experimental results show that the field oxide transistor threshold and breakdown voltages do not depend on the channel length when it changes from 1.5 to 2.51am. With increase of the field implantation dose, the threshold voltage increases while the breakdown voltage decreases. For polysilicon gate field oxide transistors a dose of 6.5• 1012 cm -2 ensures nearly equal breakdown and threshold voltages of about 15 V. This dose can be accepted as optimal for the technology considered.

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Fig. 5 Distribution of the breakdown voltage between polysilicon plate above diffusion lines. The number of the measurements is 310

Gate oxide failure along a field oxide edge has been evaluated by measuring the breakdown voltage between polysilicon plates above diffusion lines. In Fig. 5 the breakdown voltage distribution from 310 measurements is shown. Neglecting the low voltage breakdowns that most probably are due to rough defects like pin-holes this distribution has two well defined maxima - at 29 and 40 V. The breakdown voltages for all control wafers with LOCOS isolation have relatively equal values of about 40 V. It is suggested that the second maximum is caused by the same breakdown mechanism for both cases and corresponds to the intrinsic breakdown. The maximum at 29 V can be connected with the sharp step between the thin and thick oxide. Because ofthis the electric field has higher values at the end of the active regions. This leads to a clear indication of the corresponding defect related breakdown mechanism. More detailed investigations are needed in order to explain the physical reasons for the obtained breakdown voltage distributions. The results presented show that for a gate oxide thickness of 400 h this isolation technique can ensure the necessary isolation quality of the polysilicon level from the substrate and enables IC fabrication where the minimum mask distance between active regions is 1.51am. One of the main tasks of this investigation is to estimate the minimal dimensions of the active regions which can be realised by a SOLO process. The diffusion line reduction can be calculated by measuring the diffusion register currents with different widths [5]. In Fig. 6 the dependence on width of the current passing through a diffusion register is shown. The width is measured optically after silicon nitride plasma etching for both isolation techniques. The voltage between the contacts is 5 V. The lines are drawn by the least-squares method using 258 experimental points. Having in mind that the lengths and the sheet resistances of all resistors are equal the additional condition that both lines be parallel was introduced in the calculations. It is shown that the effective "bird's beak" length for the standard isolation is 0.41am. Using the SOLO process the size defined in the silicon nitride layer remains nearly the same to the end of the technological sequence. This result is in good agreement with the SEM photographs of diffusion line cross-sections. In Fig. 7 the dependence of depletion mode transistors drain current on the channel width is shown for both isolation techniques. The measurement conditions and the reduction estimation are done in the same way as described above. This shows that field implantation dose does not inflflence much the overall reduction. For this reason the values shown 15

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in Fig. 7 are the mean of all measurements. It can be seen that in comparison with the standard isolation the reduction decreases by 0.75pm which is in good agreement with the result for the diffusion lines. The size defined in the silicon nitride layer decreases by 1.1 ll~m to the end of the technological sequence. Since in this case the local oxidation reduction is minimal, this result can be connected with the diffusion of the field implantation dopants and the finite depletion region width of the channel-substrate p-n junction.

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TABLE II Threshold voltage mean values of transistors with SOLO and LOCOS isolation. The channel length is 7tam and the channel widths are 2 and 151am VT (VOLTS)

W

(lam) SOLO

LOCOS

2

0.79

1.52

15

0.67

0.68

Using the newisolation technique a significant reduction of the narrow channel effect for enhancement transistors could be achieved. In Table 2 the threshold voltage mean values of 71am channel length transistors with mask widths of 2 and 151Jm respectively are presented. It is shown that for the SOLO process the threshold voltage increase is 0.12 V which is acceptable from a practical point of view. We should point out that after silicon nitride plasma etching the narrow transistor has a width of 1.371am. Under the same conditions a transistor done with standard isolation technique is completely useless. Fig. 8 shows a polysilicon contact with a diffusion region through a contact hole in the gate oxide. C denotes the mask overlapping of polysilicon and diffusion. The minimal value of C can be estimated measuring resistor arrays with different geometries. The graphics illustrate the dependence of the failure percentage, i.e. disconnections of the arrays due to C for both isolation techniques. It is clear that SOLO allows the size of C to be reduced by 0.51am in comparison with the standard isolation. Its minimal value depends on the plasma etching reduction of the polysilicon lines and in this case is about 21am. Contacts of this type usually need great area and the possibility for its reduction is significant for circuit densification. %

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4. Conclusions

The possibilities for VLSI application of one of the simplest isolation techniques (Polysilicon Edge Sealed LOCOS) are examined. The results obtained showll~at it allows complete elimination of field oxide encroachment under the nitride mask. The leakage current and oxide integrity of the SOLO process are equivalent to those of conventional LOCOS. This makes the application of SOLO isolation possible in VLSI circuits. 5. References

[1] [2] [3] [4] [5]

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Apples, J.A., Kooi, E., Paffen, M.M., Schaterji, JJ.H. and Verkuylen, W.H.C.G., "Local oxidation of silicon and its application in semiconductor device technology," Philips Res. Rep., Vol. 25, No. 2, p. 118, 1970. Oldham, W., Shaham-Diamond, Y., Pal, P., Young, K. and Saturdja, P., "MOS isolation technology," Physics, 129 B, p. 53, 1985. Marston, A. and Anne, L., "Edge seal with polysilicon in LOCOS process," Pat. 4.435.446, USA. Burton, G., Tuntasood, P., Chien, F., Kovacs, R. and Vora, M., "New techniques for elimination of the bird's head and bird's beak," IEDM Technical Digest, p. 582, 1984. Andrews, J.M., "A lithographic mask system for MOS fine-line process development," The Bell System Technical Journal, p. 1107, April 1983.