Capacitance–voltage characterization of thin film nanoporous alumina templates

Capacitance–voltage characterization of thin film nanoporous alumina templates

Microelectronics Journal 37 (2006) 695–699 www.elsevier.com/locate/mejo Capacitance–voltage characterization of thin film nanoporous alumina template...

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Microelectronics Journal 37 (2006) 695–699 www.elsevier.com/locate/mejo

Capacitance–voltage characterization of thin film nanoporous alumina templates Biswajit Das a,*, Christopher Garman b a

Department of Electrical and Computer Engineering, University of Nevada, 5405 Maryland Parkway, Las Vegas, NV 89154, USA b Redpoint Controls, 364 Patteson Drive, Suite 279, Morgantown, WV 26505, USA Received 28 September 2005; accepted 18 December 2005 Available online 3 March 2006

Abstract This paper presents the results of capacitance–voltage characterization of thin film alumina templates fabricated on silicon substrates. Such templates are of significant interest for the low-cost implementation of semiconductor and metal nanostructure arrays, as well as for potential nanostructure integration with silicon electronics. Thin film alumina templates created on silicon substrates under different anodization conditions were investigated. Capacitance–voltage measurements indicate that the template/silicon interface, important for nanostructure integration on silicon, to be of good device quality. q 2006 Published by Elsevier Ltd. Keywords: Nanostructure integration on silicon; Nanoporous dielectric; Nanostructure C–V characteristics

1. Introduction Anodized alumina templates have emerged as an important material system for the low-cost fabrication of semiconductor and metal nanostructure arrays [1–3]. This material system uses natural self-organization for the creation of periodic arrays of nanoscale structures. The underlying principle is that when aluminum is anodized in a suitable acidic electrolyte under controlled conditions, it oxidizes to form a hydrated aluminum oxide (alumina) containing a two-dimensional hexagonal array of cylindrical pores as shown in Fig. 1 [1]. The pore diameter and the inter-pore spacing depend on the anodization conditions such as electrolyte pH, type of acid, anodization current/voltage, electrolyte temperature and the substrate parameters. The pore diameter can be varied between 4 and 100s of nanometer and the pores can be several microns deep [4–8]. Due to the excellent periodicity of the pores, and the ability to control the pore diameters, such anodized alumina films can be used as templates for the fabrication of periodic arrays of nanostructures [9]. While most of the work in this field has focused on bulk aluminum, the use of a bulk aluminum substrate precludes most photonic and electronic * Corresponding author. E-mail address: [email protected] (B. Das).

0026-2692/$ - see front matter q 2006 Published by Elsevier Ltd. doi:10.1016/j.mejo.2005.12.004

applications due to the opaque nature of the unconverted aluminum substrate, and the inability to readily integrate the nanostructure arrays with other device technologies. Therefore, direct creation of the template on the desired substrate is preferred, and thin film alumina templates are of particular importance for device applications. Such thin film templates formed on silicon substrates are of particular interest due to their promise for the integration of nanostructure devices with silicon electronic devices. For such integration, the alumina/ silicon interface will play an important role, investigation of which is the objective of this paper. Capacitance–voltage (CV) characterization is a widely accepted means of testing metal–insulator–semiconductor (MIS) structures and for determining device parameters such as carrier density, Fermi level, flatband voltage and threshold voltage. These values not only serve as the basis for other calculations, but also provide valuable data regarding the insulator/semiconductor interface. The typical CV characteristics of an MIS capacitor formed on a p-type semiconductor substrate is shown in Fig. 2; the inset shows schematic crosssection of the device as well as the CV measurement set-up. For negative bias voltages, the semiconductor surface remains in accumulation and the capacitance Co is determined by the properties of the insulator layer. For positive voltages, the semiconductor surface near the insulator becomes depleted, and the device capacitance is determined by both the insulator and the depletion layer thickness. Since, the depletion layer

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B. Das, C. Garman / Microelectronics Journal 37 (2006) 695–699 1.5E-07

(a)

1.0E-07

Current (A)

5.0E-08 0.0E+00 -6

-4

-2

-5.0E-08

0

2

4

6

-1.0E-07 -1.5E-07 -2.0E-07 -2.5E-07 -3.0E-07

Voltage (V) (b)

1.6E-05 1.4E-05 1.2E-05

Current (A)

1.0E-05 8.0E-06 6.0E-06 4.0E-06 2.0E-06 -20

-15

-10

0.0E+00 -5 0 -2.0E-06

5

10

15

20

-4.0E-06

Voltage (V)

Fig. 3. Current–voltage (IV) characteristics of (a) pore-widened and (b) pore non-widened samples. Anodization current density: 30 mA/cm2. Fig. 1. Top and cross-sectional views (schematic) of hexagonal array of pores formed in porous alumina template.

thickness increases with increasing positive voltage, the overall capacitance decreases with increasing positive voltage. This process continues until the bias voltage reaches the threshold voltage VT, when the insulator/semiconductor interface becomes inverted. Under inversion, the depletion layer thickness becomes constant at the maximum value, and the overall capacitance becomes constant at Cinv. Valuable information about the insulator and the insulator/semiconductor interface can be derived from the CV characteristics and the magnitudes of Co, Cinv and VT.

AC

C0

DC

1200

p-Si

Capacitance (pF)

Accumulation

ion

let

p De

800

400 Inversion

-6

-4

-2

0

0

2

VT

4

C inv

6

Voltage (V)

Fig. 2. Typical capacitance–voltage characteristics of a metal–insulator– semiconductor (MIS) structure fabricated on p-type semiconductor substrate. The inset shows a typical device cross-section and the measurement set-up.

2. Experimental procedure and results A number of aluminum/porous alumina/p-Si MIS capacitors were fabricated using the following technique. P-type silicon substrates were first summa-cleaned, then immersed in a 1% HF bath, rinsed, and dried in N2. Then, a 100 nm layer of Al was sputter deposited on the back of the wafer, followed by annealing at 450 8C for 30 min to form an ohmic back contact. Next, a 100 nm layer of Al was deposited on the top of the wafer, which was then annealed at 400 8C for 30 min to ensure good adhesion. The wafers were then anodized in 20% sulfuric acid at current densities of 15, 20 and 30 mA/cm2. Some of these wafers were then pore-widened in 5% phosphoric acid for either 3 or 6 min durations. The purpose of pore widening is to remove any remaining barrier layer (alumina) at the alumina/silicon interface, as well as to remove impurity ions left over from the anodization process. Finally, a number of Al contacts, each 1.59 mm in diameter, were sputter deposited through a shadow mask on top of the template to create the capacitors. First, current–voltage (IV) measurements were performed on each capacitor sample to determine the range of bias voltages to be used for CV measurements. Typical current– voltage results for pore-widened and non-widened samples are shown in Fig. 3(a and b), respectively. On each wafer, the five devices with the lowest leakage currents were selected for CV measurements. Capacitance–voltage measurements were performed at a frequency of 1.0 MHz. The bias voltage was varied between K5 and C5 VDC for pore-widened samples and from K15 to C15 VDC for non-widened samples. For each of the

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Threshold Voltage Distribution 4.0 No Widening 3.5

3 min

Threshold Voltage (V)

3.0

6 min

2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 10

15

20

25

30

35

Anodization Current Density (mA/cm2 )

Fig. 5. Threshold voltage distribution for the Al/alumina/p-Si capacitors formed under different fabrication conditions.

selected devices, multiple CV scans were taken and the data were averaged to provide a characteristic profile for a single device. The CV measurements were carried out in the dark to avoid photocurrent effects. The results of CV measurements on samples anodized at 15 mA/cm2 are shown in Fig. 4(a–c), respectively. The samples created with 20 and 30 mA/cm2 showed similar characteristics. 3. Analysis and discussions The CV data shown in Fig. 4(a–c) suggest that the alumina/ silicon interface to be of good quality as indicated by the formation of accumulation, depletion and inversion layers, as expected for an MIS structure (Fig. 2). This is encouraging for the future integration of nanostructure devices on silicon, where the interface is expected to play an important role. The CV data were analyzed to calculate device parameters such as theoretical carrier density, threshold voltage, and flatband voltage. The carrier density of the substrate was calculated and compared with the known substrate density for verification, which matched very well. The threshold voltages for each capacitor were obtained from the CV data using the relationship VTH Z VðCinv C ðCo KCinv Þ 0:05Þ; this is the voltage at which the capacitance drops to 5% of the difference between its maximum and minimum values. The results of the calculations are shown in Fig. 5. For each

VFB Z VðC0 KðCo KCinv Þ 0:05Þ; this is the voltage at which the capacitance drops to 95% of the difference between its maximum and minimum values. The results are shown in Fig. 6. Although the flatband voltage shows a large distribution, an average value for the porewidened samples was calculated to be K3.29 V. It can be seen

Flatband Voltage Distribution 0.0 -1.0

Flatband Voltage (V)

Fig. 4. Capacitance–voltage characteristics for Al/alumina/p-Si anodized at 15 mA/cm2: (a) pore-widened for 3 min; (b) pore-widened for 6 min; The inset in (a) shows the devices used in the experiments.

anodization current density, the threshold voltages are plotted for different capacitor pad of the various samples: those not pore-widened, those widened for 3 min, and those widened for 6 min. It may be noted that pore widening has a significant effect on threshold voltage distribution for samples anodized at 15 mA/cm2. This is an important observation since lower current densities are typically used to obtain smaller pore diameters. For samples anodized at 20 and 30 mA/cm2, the effect of pore widening on the threshold voltage distribution is not as obvious. However, pore widening of 3 min appears to produce lower variations in threshold voltages. The CV data was also used to calculate the flatband voltages using the expression

-2.0 -3.0 -4.0 -5.0 -6.0

No Widening

-7.0

3 min 6 min

-8.0 -9.0 10

15

20

25

30

35

Anodization Current Density (mA/cm2)

Fig. 6. Flatband voltage distribution for the Al/alumina/p-Si capacitors formed under different fabrication conditions.

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Table 1 Experimentally determined accumulation capacitance and effective dielectric constants for the samples used in the experiments Current density (mA/cm2)

Not porewidened

Pore-widened 3 min

Pore-widened 6 min

15

CoZ174 pF 3rZ1.98 CoZ143 pF 3rZ1.63 CoZ178 pF 3rZ2.02

CoZ300 pF 3rZ3.42 CoZ260 pF 3rZ2.96

CoZ300 pF 3rZ3.42 CoZ300 pF 3rZ3.42 CoZ320 pF 3rZ3.65

20 30

from Fig. 3 that the flatband voltage distribution is significantly reduced for the pore-widened samples. The improvement in VFB for the pore-widened samples is believed to be due to the removal of the impurity ions left by the anodization process. It is encouraging to note that similar characteristics have also been observed in capacitors formed on AlO:N insulators created by the oxidation of AlN thin films on silicon [10]. The AlO:N insulators, which are non-porous, are being investigated as alternatives for SiO2. A flatband voltage of VFBZK2.723 V was obtained in [10]. It is, however, important to note that the devices investigated in this work use porous alumina structures created by electrochemical means, rather than crystalline arrangements grown by epitaxial methods. After considering Co of each capacitor, it is simple to calculate the dielectric constant for each sample using the following relationship 3Z

Co tox 3A

where Co is the oxide capacitance (F), tox is the oxide thickness (m), and A is the area of the top contact (m2). The resulting calculations are shown in Table 1. From Table 1, it is interesting to note that the relative dielectric constant increases for samples that have been pore-widened. This indicates that the pore widening process changes the pore geometry. Although pore widening slowly increases the diameter of the template pores, the oxide capacitance (and therefore the relative dielectric constant) increases, which seems to be contradictory at first. We believe that the explanation for this phenomenon is that the plates of the capacitor (the Si substrate and the Al top contact) are closer together in pore-widened samples. The reason for this is that when the Al top contact is sputtered onto non-widened samples, it creates a semi-uniform covering across the pores. In widened samples, however, impurities inside the pores are drastically reduced, and the Al top contact deposits partially inside the pore during the sputtering process, as schematically shown in Fig. 7. However, more experimental investigation is necessary before this conjecture could be confirmed. While cross-sectional imaging of the samples was made difficult by the small dimensions of the pores, and the very high resistivities of the alumina layers (which caused charging uring scanning electron microscopy), we have carried out the following analysis that provide some insight into the

Impurity Ions

Al2O3

Al

Cal C air

Si

Unwidened Al2O3

Al

Cal Cair

Si

Widened

Fig. 7. Schematic cross-sections showing the expected effect of pore widening on the Al/alumina/p-Si capacitors used in the experiments.

characteristics of the porous alumina layer. Although the thin film alumina template is a complex porous structure, the total accumulation capacitance Co may be approximated as two capacitances in parallel: Co Z Cair C Cal where Cair is the capacitance due to the air-filled pores, and Cal is the capacitance due to the porous alumina layer (please refer to Fig. 7). Since the walls are constructed of alumina, with a dielectric constant of approximately 3alZ9.7, and the pores are filled with air, which, by definition, has a dielectric constant of 3airZ1.0: Co Z

3air 3o Aair 3al 3o Aal C tair tal

It is known that the porosity, P (ratio of pores to total area), is quite high. It is also known that the thickness of the alumina layer after anodization (tal) is at least 200 nm from fabrication parameters. And finally, it is known that the thickness of the air layer should be less than that of the alumina layer. If these three quantities are considered across a short range, viable measurements of pore dimensions may be estimated using the above relationship. These calculations were performed and

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deposited on top of the pores, enters the pores by no more than 100 nm. In summary, we have performed capacitance–voltage measurements on thin film alumina templates fabricated on silicon substrates under various anodization conditions. The CV characteristics show distinct differences for pore-widened and pore non-widened samples. The CV characteristics indicate that the alumina/silicon interface is of good device quality as suggested by the formation of accumulation, depletion and inversion layers. A simple analysis of the CV data was carried out to validate the experimental results and to obtain an approximate estimate of the template porosity. Acknowledgements The authors would like to acknowledge P. Sines, S. Nistala and S. McGinnis for help with device fabrication and characterization. Fig. 8. Pore geometry analysis for the alumina template anodized at 15 mA/cm2.

References

Fig. 8 shows the resulting plots for samples anodized at 15 mA/ cm2. From Fig. 8, it can be seen that for a selected thickness of the alumina and air layers, the porosity of the template increases with an increase in anodization current density. Porosity is expected to increase linearly as a function of anodization potential, as indicated by other studies. The region of valid estimation is contained in the trapezoid bounded by the conditions xO200!10K9, x!300!10K9, y!x, and yO0. By examining these graphs, it can be seen that the porosity in each of the pore-widened samples is at least 77%, which is close to what is expected for the anodization parameters used. It is also interesting to note that, as the thickness of the alumina is increased, the thickness of the air layer approaches an asymptote near 100 nm. Therefore, regardless of the actual porosity, the air layer is at least 100 nm thick. It may thus be inferred that the aluminum top contact, which is sputter

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