Chapter 4 MOS Transistors

Chapter 4 MOS Transistors

CHAPTER 4 MOS Transistors Marvin H . White* . . . . . . . . . . . . . . 11. MOS CAPACITORS . . . . . . . . . . 2. Theory of the M O S Capacitor . . ...

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CHAPTER 4

MOS Transistors Marvin H . White*

. . . . . . . . . . . . . . 11. MOS CAPACITORS . . . . . . . . . . 2. Theory of the M O S Capacitor . . . . . . 3. Experimental C-V Characteristics . . . . . 111. MOS TRANSISTORS . . . . . . . . . . 4. Deuice Structure . . . . . . . . . 5. Physical Device Theory . . . . . . . 6 . Small-Signal Characteristics . . . . . . I . Switching Characteristics . . . . . . . 8. Fabrication and Stabiliiy Considerations . . . IV. MOS TRANSISTOR CIRCUITS . . . . . . . 9. P-Channel MOS-FET Circuits . . . . . 10. Complementary MOS-FET Circuits . . . . LISTOF SYMBOLS . . . . . . . . . . I. INTRODUCTION

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1. General Considerations .

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203 203 206 206 217 232 232 234 241 245 249 260 260 264 269

I. Introduction 1. GENERAL CONSIDERATIONS

In the last two decades, the semiconductor surface has been the subject of many investigations. In 1948, Shockley and Pearson' attempted to realize a semiconductor amplifier by modulating the semiconductor surface conductance with an electric field normal to the surface. This electric field was applied across a metal electrode-dielectric-germanium sandwich, the germanium serving as the other electrode. The low modulation that they observedla was explained (in terms of a model proposed by Bardeen') as arising from a high concentration of surface states (10'5/cm2) at the * Present address: Westinghouse Electric Corporation, Advanced Technology Laboratories,

Baltimore, Maryland. W. Shockley and G. L. Pearson, Phys. Rev. 74,232 (1948). '"Approximately 90 % of the induced surface charge in the germanium resided in bound states at the germanium surface, while only 10% of the induced charge was mobile. J. Bardeen, Phys. Rev. 71, 717 (1947).

I

203

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MARVIN H. WHITE

semiconductor surface. Although these initial attempts to realize a semiconductor amplifier were unsuccessful, this method of surface conductance modulation provided the basis for jeld-efSect experiments3 during the 1950’s. In this period, the semiconductor surface was studied using the field-effect electrode as an experimental instrument to measure surface conductance. These experiments were performed on chemically etched germanium and silicon surfaces which had been exposed to various surface treatments such as heating in gaseous ambients, vacuum baking, chemicals, and even ion-bombardment techniques. The condition of the semiconductor surface was characterized by the measurement of surface conductance. The large number of surface states, combined with the lack of surface reproducibility and stability, hindered the development of a semiconductor amplifier operating on the “field-effect principle.” With the advent of planar diffusion technology, it has been possible to obtain low surface state densities ( 10’‘/cm2)which may be prepared in a stable and reproducible manner. The thermally oxidized silicon surface was employed by Kahng and Atalla4 in 1960 to realize a surface field-effect transistor. The operation of this device depends upon the modulation of the semiconductor surface conductance when an electric field is applied across a metal-oxide-semiconductor (MOS) structure. The electrical characteristics of this MOS field-effect transistor (FET) were first analyzed in detail by Ihantola. His model of the MOS-FET included the spatial and voltage-dependent bulk charge of the semiconductor ; however, he neglected the fixed charges within the oxide (i.e., oxide charge), the interface states located at the siliconsilicon dioxide interface, and the metal-semiconductor work-function difference. The characteristics of these devices were studied by Borkan and Weimer6 in 1963, who extended Ihantola’s work, by Hofstein and Heiman7 in 1963, who constructed the forerunner of the integrated-circuit MOS transistor, and by Sah8 in 1964. who considered a constant bulk-charge

-

W. H. Brattain and J. Bardeen, Bell Syst. Tech. J . 32, 1 (1953). See also, for general reference: A. Many, Y. Goldstein, and N. B. Grover, “Semiconductor Surfaces.” Wiley, New York, 1965 ; “Semiconductor Surface Physics” (R. H. Kingston, ed.). Univ. of Pennsylvania Press, Philadelphia, Pennsylvania, 1957; J. T. Law in “Semiconductors” (N. B. Hannay, ed.),Chap. XVI. Reinhold, New York, 1959. D. Kahngand M . M. Atalla, unpublishedcommunication, 1960.M . M. Atalla, E.Tannenbaum, and E. J. Schreibner, Bell, Syst. Tech. J . 38, 749 (1959). H. K. J. Ihantola, unpublished communication, 1961 ; H. K. J . Ihantola and J. L. Moll, Solid State Electron. 7,423 (1964). H. Borkan and P. K. Weimer, RCA Rev. 24, 153 (1963). S. R. Hofstein and F. P. Heiman, The Silicon Insulated Gate Field Effect Transistor, Int. Electron Device Meeting Washington, D.C.. October, 1962; S. R. Hofstein and F. P. Heiman, Proc. IEEE 51, 1190 (1963). C. T. Sah, I E E E Trans. Electron Devices ED-I 1, 324 (1964).



4. MOS TRANSISTORS

205

distribution to develop the MOS device current-voltage characteristics. Theoretical and experimental studies by Sah and Pao' in 1966 have resulted in an improved theory for the MOS-FET by the inclusion of the spatial and voltage-dependent bulk charge of the semiconductor. The development of the MOS-FET is a direct outgrowth of an intensive program in applied surface research. The underlying factor in this research is the necessity of obtaining reproducible and stable surface characteristics with low surface state densities. The metal-oxide-semiconductor (MOS) system has been found by Grove et a1.l' to be a useful tool in the study of thermally oxidized silicon surfaces. With this experimental instrument, the surface potential or surface state density can be determined by comparing experimental and theoretical capacitance-voltage (C-V) characteristics. The MOS system in this manner is used as a voltage-dependent capacitor in which a two-terminal analysis of the oxidized silicon surface is performed. While the MOS capacitance provides a method to study the silicon surface with a variable reactance,'O" the MOS-FET device enables the device physicist to examine the variations in surface conductance. We next review the theory of the voltage-dependent MOS capacitor operating under the various modes of accumulation, depletion, or inversion of the semiconductor surface. Fabrication and the experimental determination of C-V characteristics are discussed in terms of a representative fabrication process. Then we discuss general device theory and the fabrication and experimental evaluation of n- and p-channel MOS-FET's for a representative fabrication process. The small-signal amplifier and switching characteristics of MOSFET's are also discussed. The final portion of the chapter is devoted to the application of p-channel and n-channel enhancement-mode MOS-FET's in digital or switching-type circuits.

FIG. 1. Siliconsilicon dioxide-aluminum system. C. T. Sah and H. C . Pao, l E E E Trans. Electron Devices ED-13, 393 (1966). A. S. Grove, B. E. Deal, E. H. Snow, and C. T. Sah, unpublished communication, 1Y64; Solid State Electron. 8, 145 (1965). '"The MOS capacitor has been employed as a variable conductance to study low surface state densities in the thermally oxidized Si-SiO, system. This conductance exists because of the surface state lifetime, which leads to a loss mechanism. E. H. Nicollian and A. Goetzberger, Bell Syst. Tech. J . 46, 1055 (1967). lo

206

MARVIN H. WHITE

11. MOS Capacitors

2. THEORY OF

THE

MOS CAPACITOR"-^^

The mathematical development of the general theory of the MOS capacitor is related to the operation of the MOS-FET structure. Consider an MOS capacitor comprising a p-type silicon semiconductor, a silicondioxide insulating layer, and an aluminum metal electrode as shown in Fig. 1. This structure may be examined under the application of a gate voltage V, applied to the aluminum electrode with respect to the semiconductor back contact. If a negative bias is applied to the aluminum electrode, then the holes or majority carriers in the p-type silicon will be attracted to the Si-SiO, interface. This process is called accumulation and the resultant capacitance per unit area is simply the capacitance of the SiO, dielectric, c o

=

KoEo/tox3

(1)

where K Ois the dielectric constant, E~ the permittivity of free space, and to, the oxide thickness. Figure 2(a) illustrates the accumulation of majority carriers at the Si-SiO, interface for a p-type silicon semiconductor. As the gate voltage is made positive with respect to the semiconductor, the holes are repelled from the Si-SiO, interface and a depletion or space-chargeregion forms as indicated in Fig. 2(b).When the depletion region occurs at the semiconductor surface, the total capacitance of the MOS system is determined by the series combination I + c, c, i-css’

_1 - 1 c-

lobW. Shockley, “Electrons and Holes in Semiconductors,” pp. 302-308. Van Nostrand, Toronto, New York, and London, 1950. ‘“‘the extrinsic Debye length LD* is perhaps a more meaningful description of the extent of the

space-charge region into the semiconductor at flat-band :

and the flat-band capacitance C,, = K,co/LD*. J. L. Moll, IRE WESCON Convention Record, pt. 3, 32 (1959). l2 R.Lindner, Bell Sysr. Tech. J . 41, 803 (1962). L. M. Terman, Solid State Electron. 5, 285 ( I 962). l4 K. Lehovec, A. Slobodskoy, and J. L. Sprague, Phys. Status Solidi 3, 447 (1963). l 5 R.H. Kingston and S. F. Neustadter, J. Appl. Phys. 26, 718 (1955). l 6 D. R. Frankl, Solid State Electron. 2, 71 (1961). l 7 C. G. B. Garrett and W. H. Brattain, Phys. Rev. 99, 376 (1955). l 8 A. S. Grove, E. H. Snow, B. E. Deal, and C . T. Sah, J. Appl. Phys. 35,2458 (1964). ” W. L. Brown, Phys. Rev. 91, 518 (1953). 2o C. E. Young J . Appl. Phys. 32, 329 (1961).

7

(Metal)

'

EC

Ei

EF Ev

(a) Accumulation of Majority Carriers Near Surface +e
( b ) Depletion

of Majority Carriers From Surface

(c) Inversion Accumulation of Minority Carriers Neor

FIG. 2. Energy bands and charge distribution in an MOS structure under various bias conditions in the absence of surface states and work function difference. (After Grove et al.'')

4

208

MARVIN H. WHITE

where C, = -dQ,/d4, is the space-charge capacitance and C,, = -dQ,,/d4, the capacitance associated with surface states. Here, Q , and Q,, are the total semiconductor charge density and surface-state density, respectively, and 4sis the surface potential referenced to the intrinsic Fermi level in the bulk semiconductor. For a large positive bias, the electrons or minority carriers are attracted to the surface, forming an inversion layer beneath the SiO, at the interface as shown in Fig. 2(c). During the formation of the depletion region, the semiconductor charge density Q , is the uncompensated ionized acceptor concentration ;however, at the onset of inversion, a portion of this total charge will consist of electrons in the inversion layer. For increasing gate voltages, corresponding to strong inversion, a larger fraction of this total charge will come from the electron charge in the inversion layer. It is instructive to note that the total capacitance of the MOS structure will deviate from the oxide capacitance C, only to the extent that the surface potential 4, can respond to the applied signal. In order to understand the capacitance-voltage characteristics, the ideal MOS structure is analyzed, where it is assumed that surface states and metalsemiconductor work-function differences are absent. Then, the deviation of experimental capacitance-voltage (C-V) characteristics from the theoretical C-V characteristics is attributed to these neglected quantities. In the analysis to follow, it is assumed that the dc bias is varied to ensure an equilibrium charge distribution'4*'5*17 in the semiconductor. In the analysis, it is assumed that the generation and recombination of minority carriers near the semiconductor surface is such that np = ni2 (i.e., thermal equilibrium). If a lateral surface current were to exist in the inversion layer as in the MOS-FET structure, then the concept of the "quasi-Fermi level" for the minority carriers would be required. The total net charge Q , within the semiconductor consists of bulk space-charge QB and inversion region charge Q, (electron charge),

Q, = Q B + Q,

=

JOm

P(X) dx,

(3)

where P(4

= 4cp

-n

+ N,

- NAI

(4)

is the charge density determined by the algebraic sum of fixed and mobile charge densities. The quantity IN, - N,I is the uniform doping level in the semiconductor and the point x = 0 corresponds to the Si-SiO, interface. At thermodynamic equilibrium with a nondegenerate semiconductor, the mobile carrier densities are given as" p

=

ni exp(U , - V ) = po exp( - U ),

n = ni exp(U - U,)

=

no exp(U ),

(5)

4.

209

MOS TRANSISTORS

where U , is the normalized Fermi potential, given as =

uF

q&F/kT

=

(54

(q/kT)[(Ei - E F ) / g l

and U is a normalized electrostatic potential given by the expression

u = q+/kT

= ( q / k T )[ E i

-

(5b)

Ei)/ql2

where Ei and Ei are the bulk intrinsic Fermi level and the intrinsic Fermi level in the space-charge region, respectively. Equation ( 5 ) follows directly by the substitution of Eqs. (5a) and (5c) into the carrier density relationshipstob p

=

n, exp(E, - E,)/kT,

n

=

n, exp(E, - E,)/kT.

(54

Essentially, Eq. ( 5 ) expresses the carrier densities with the intrinsic bulk Fermi level Ei as the reference electronic energy. The doping level may be related to the Fermi potential by using the condition of charge neutrality in the bulk semiconductor. Combining Eqs. (4) and ( 5 ) with U = 0 and p = 0 yields N , - N, = 2ni sinh U , . (6) Poisson's equation for the space-charge region of the semiconductor is given as d%#/iix2 =

-

(7)

p(x)/K,Eo,

where K , is the dielectric constant of the semiconductor. Use of Eqs. (4H6) enables Poisson's equation to be written in the form

d2U/dx2 = (l/L,')[sinh ( U - U,) where L, is the intrinsic Debye length"' the equation

+ sinh U , ] ,

of the semiconductor, defined by (9)

(K,~,kT/2q'n,)'~~.

L,

(8)

Integrating from the bulk semiconductor toward the Si-SiO, surface and using the boundary conditions U(X = 0) =

us,

U ( x = co) = 0,

au

-(x ax

=

co) = 0

yields the expression

P(-)~ au lo xd(x) au 1 2

ax

=

au/axa~

=

&lou[sinh(U - U,)

+ sinh U F ] d U

210

MARVIN H . WHITE

and evaluation of the electric field at the surface ( U

=

U s )yields

/ s (ensures the physically meaningful sign. The function where the factor U s / U F(U,, U , ) = {2[cosh(U, - V,)

+ U,sinh

U , - cosh UF]}''2

(12)

has been in the literature with the surface potential referenced to the bulk Fermi level.2oaThe net charge in the semiconductor is, by Gauss' law, U Q , = - K ,cotr. = -2QDF(Us,

I us1

UF)?

(13)

where Q, = f<,&,kT/qL,.The part of Qs that is due to the electrons within the inversion region is calculated as follows :

where xi is the position in the semiconductor where Ei = E , . Substitution of Eqs. (5) and (10) into Eq. (14) yields

The magnitude of the total charge induced in the silicon semiconductor at the onset of inversion IQ,(inv)l can be calculated as a function of the total impurity concentration IN, - N,J by setting +s = $F in Eq. (13) and using Eqs. (6),(9), and (12). The results are shown in Fig. 3, where the corresponding surface field 5, is included in the right-hand scale. Equation (15) has been numerically calculated l o for a specified bulk impurity concentration IN, - N,I and a given value of the surface potential. The results of these calculations are shown in Fig. 4, in which the magnitude of the inversionlayer charge is given as a function of the total charge induced in the silicon semiconductor. Inspection of Eqs. (1 3) and (15) for large values of the surface potential 4sindicates (as seen in Fig. 4) that Q, -+ Q,. It is often desirable to approximate the behavior of the semiconductor surface by the use of the depletion approximation'' used in p n junction theory. When the semiconductor surface is in the depletion region (Q, = 0), ""The transformation between the normalized electric field function of Eq. (12), designated as F(U,, UF),and the function tabulated in the literature, which we shall designate here as F(U,’, UB), is given as U , = - U,, Us' = U , - UF.

4. MOS TRANSISTORS p I

10

I

I l l

I

(n-Type Si)ohm-crn

I

I1 I

I

211

1

I

0.1

I

1

I

0.01 I I

I

E I06

N I

E

I

-

-

v

lo5 E

> 0

-I

I I1111111 I l l I

lII11111 I I1111111 I I l l 1 I

I I I I

100

I 0

p

I

I

I

IIIIOII I 1

0. I

I

I I

lo4

d

d

IIIIILI

( p - Type Si ) (ohm-cm)

Fie. 3. The magnitude of the total charge induced in the silicon at the onset of inversion, IQ,(inv)l, as a function of the surface impurity concentration IN, - N,I. A scale giving the corresponding surface field 5, is also included ;this field is given by Gauss's law, ts= Q,(inv)/K,co. (After Grove and Fitzgerald.)'Ob

the semiconductor surface charge is the bulk space charge, Q s = QB

= -~

N -AND)%

(16) where xd is the width of the depletion region as shown in Fig. 2(b). With this distribution, Poisson's equation [Eq. (7)] may be integrated to obtain

4

=

$sL1

-

(x/xd)12?

(17)

where the surface potential &, which determines the amount of energyband bending, is determined by the expression

4s =dNA

-

N&d2/2Ks&,.

(18)

The depletion layer will spread until the bands have bent sufficiently to cause surface inversion at $s = (bF. The depletion approximation fails when the inversion-layer charge becomes appreciable in comparison to the bulk charge. When this occurs, the depletion-layer width reaches a maximum value xd(max). This maximum width may be estimated by employing the criterion for strong in v er~ io n ,'~ $,(inv) = 2&, which requires that the minority carrier density be equivalent to the bulk-charge density NA - N,. 'ObA. S . Grove and D. J. Fitzgerald, I E E E Trans. Electron Devices ED-12,619(1965).

212

MARVIN H . WHITE

FIG.4. Equilibrium characteristics of an inverted semiconductor surface ; the magnitude of the charge of the minority carriers within the inversion region as a function of the magnitude of the total charge induced within the semiconductor (silicon at 300°K). The parameter Us(=qr$,/kT) is the normalized surface potential. (After Grove et d.")

Thus, the maximum depletion-layer width is obtained from Eq. (IS), It is interesting to compare the diffused n + / pjunction with the MOS surface induced n'/p junction. In the former case, the depletion layer results from a metallurgical junction obtained from diffusion of impurities into the semiconductor. The MOS structure operating under strong surface inversion has a field-induced junction. In this structure, the depletion layer reaches a maximum value, while in the metallurgical junction, it continues to spread as a function of the applied reverse bias. The applied gate voltage V, may be related to the parameters of the MOS structure as shown in Fig. 5. The surface state density may in practice consist of interface states and oxide charge; however, in this section we will consider an effective Qss located a t the Si-SiO, interface and make no distinction

4. MOS TRANSISTORS

I1

I

Ij 4 M

213

A (Metal)

FIG.5. The energy bands and charge distribution in an MOS structure under applied gate bias and with the effects of surface-state charge and work-function difference included.

between these two entities. Figure 5 illustrates the energy bands at zero gate bias (dashed lines and zero subscript) and under an applied gate bias V,.

+ 4 s + 4MS7

(20)

+ Qss + Q, = 0 ,

(211

vG =

0‘

where &S dM - [x + (E,/2q) + &] is the metal-semiconductor workfunction difference, with x the electron affinity of the semiconductor. Gauss’ theorem requires QG

and, using the relation QG = CoVo,Eqs. (20) and (21) may be combined to yield VG -

~

M

S

( Q ~ C O=)d5 - ( Q , / ~ o ) =

(22)

where Vis the theoretical gate voltage in the absence of surface states and metal-semiconductor work-function difference (i.e., dMS= Q,, = 0). From

214

MARVIN H. WHITE

Eq. (22), the threshold voltage for surface inversion is VT =

2#F

+ #m

- [(Qs,

+ QJ/col.

(23)

~ ~strong The value of &(inv) at the onset is g5s = # F ; however, #s = 2 4 for inversion2' is used in Eq. (23). An experimental quantity of particular interest is the "flat-band voltage" obtained by requiring #, = 0 in Eq. (22), which yields

V,, = cbw - [Qd4S= O)/Col.

(24)

If the minority carriers can follow the applied signal,2'a*b then the spacecharge capacitance can be calculated using the equilibrium t h e ~ r y . ' ~ . ' ~ - ' ~ , ' ~ Using Eq. (1 3), the so-called "low-frequency" capacitance associated with the semiconductor surface is calculated as

[

dQ U s sinh(U, - U,) C,(low-freq) = -2 = ~

IUSI

F(Us,

+ sinh U ,

uF)

lcD?

(25)

where C, = K,co/LD. The "high-frequency" C-V characteristics result when the minority carriers are unable to follow the applied signal frequency. If the charge in the inversion region is assumed to be independent of surface potential variations, then the high-frequency space-charge capacitance becomes C,(high-freq) =

KsEO --

where use is made of the charge distribution of Eq. (16). Thus, for a choice of silicon resistivity, which determines + F , and a specified oxide thickness to,, the theoretical C-V curve for the MOS structure may be constructed.2'c'd Figure 6 illustrates the determination of three C-V curves for the particular zL The value of $,(inv) = & is referred to as the intrinsic threshold voltage, which may be written as VTi = dF &,s - [(Q,, + Q,)/C,]. The intrinsic threshold voltage is readily identifiable on the C-V curves in contrast to the threshold voltage at strong inversion. since the latter is near the minimum of the high-frequency C-V curve, where interface states

+

may be large in number. ""This is determined by the frequency of measurement and the generation-recombination relaxation times of minority carriers, since the majority carriers can be removed from the bulk semiconductor with a time constant of the order of the dielectric relaxation time (1O-l' sec). 'lbIt is assumed that the minority carriers can accumulate at the surface in the inversion region. If these carriers cannot accumulate due to a rapidly varying dc bias or "leaky oxide," then the so-called depletion capacitance occurs.'".' ' "'The high-frequency capacitance plateau in the strong inversion region (& > 2&) is determined by Eq. (26); however, the transition between depletion and strong inversion cannot be described accurately by Eqs. (18) and (19). which neglect the formation of the inversion layer.

4. MOS TRANSISTORS

215

dopant levels indicated on the curves. In the construction of these particular curves, an oxide thickness to, = 1000 is used and the total capacitance is normalized to the oxide capacitance C,. The surface potential @ s is a running parameter representing the various conditions of energy-band bending at the Si-SiO, interface. In comparing the experimental C-Vcurve to the theoretical C-Vcurve (note, for example, Fig. 8), the two curves are plotted on the same axes and the voltage separation A V = V(theor) - V,(exp) is attributed to the metal-semiconductor work-function difference and surface states. In addition to the equilibrium C-V characteristics there are nonequilibrium or "pulsed" capacitance-time (i.e., C-t) The nonequilibrium C-t characteristics are measured with the application of a voltage step to drive the semiconductor surface from a state of accumulation at t = 0 - to a deep-depletion condition at t = Ot. Subsequently, during the duration of the voltage step, the depletion region collapses to an equilibrium state of heavy inversion through the net thermal generation of minority carriers in the depletion region (i.e., the n p # ni2). Differential capacitance is measured in pulsed C-t characteristics as well as in the equilibrium C-V characteristics. A simplified analysis of the C-t characteristics may be performed for the MOS structure by equating the time rate of change of minority carrier charge Q, to a bulk and surface component as

dQ,/dt = {4ni[xd - Xd(maX)I/Tg}+ qflis (264 where xd(t)is the instantaneous depletion layer width, zg the bulk-generation lifetime, and S(t) the surface recombination velocity. The applied gate voltage step V, may be obtained from Eqs. (16), (18), and (22) as a function of the depletion layer width xd(t). Differentiation of V, for t > O+ (i.e., This has been discussed by C. T. Sah, Solid State Electronics Lab. Tech. Rep. No. 1, University of Illinois, Urbana, Illinois, December 1964. With the use of Eqs. (3), (4),and (16) and the assumption aQn/d+, = 0, an effective width may be defined as follows: -Y(NA-

=Y

lo*

[ P - (NA -

NJ1d x

Use of Eqs. (5), (6), and ( 1 1 ) permit the width to be written in the form us

xd

=

L,jo

(1 - r-")dU/F(U, U F ) .

Once the effective width is determined from the above equation, it may be inserted in Eq. (26) to calculate the high-frequency capacitance as a function of surface potential U s . 21dldealtheoretical low-and high-frequency C-V curves for various oxide thicknessesand background concentrations may be found in A. Goetzberger, Bell. Sys. Tech. J . 45, 1097 (1966). M. H. White and J. R. Cricchi, Solid Sfate Electron. 9,991 (1966). 22aM. Zerbst, 2. Angew. Phys. 22, 30 (1966). 22bD. K. Schroder and H. C. Nathanson, Solid State Electron. 13, 577 (1970). '*T.Jund and R. Poirer, Solid State Electron. 9, 315 (1966).

''

--

Depletion of Holes from SiO, - Si lnterfoce

0

A

L

---*---,,,

Np,= 5.5 x 10 l6

LOW Frequency Theory

High Frequency Theory Note: All Curves Constructed Assuming Tax ( Oxide Thickness) = IOOOA

-6

?

-5

-4

-3

0.6--

I

-2

-1

0

v m = +$

-Qs/C0

+I

+2

+3

+4

+5

+6

+7

= VG

FIG.6. Theoretical C-V curves for p-type silicon substrate. (After White and Cricchi.2Z)

+8

I

+9

4.

217

MOS TRANSISTORS

dl/,/dt = 0) with the assumption Q,, # Q,,(t) yields the expression dQn - - q(NA - N,) dt and the instantaneous depletion layer capacitance C, = K,&&d. Combining Eqs. (26), (26a), and (26b) yields the pulsed capacitance equation

]

=

-(NA

niCo N,)C,

-

["

C

-11,

(26c)

+

C,) and C , = C,C,/(C, + Cs). C, is the equilibrium where C = c,cd/(C, depletion layer capacitance in the heavy inversion state. Substitution of the identity co2d C into Eq. (26c), with the assumption of low surface recombination velocity, yields the expression for the bulk generation lifetime zg = 2niC,m/(N, - N,)C,,

(264

where

is the slope of the linear portion of the Zerbst plot.22aComputerized datareduction techniques22b are employed to generate a plot of [(C,/C) - 13 versus d(C,/C)'/dt (i.e., a Zerbst plot) and to calculate the bulk generation lifetime zg and the surface recombination velocity S ( t = 0') of the initially depleted surface.

3. EXPERIMENTAL C-V CHARACTERISTICS It is important in the fabrication of MOS-FET devices to obtain a low efectiue surface-state charge density Q,, that is both stable and reproducible. The experimentalist requires a simple instrument to examine the surface of the semiconductor as it is subjected to a variety of fabrication steps. If the only method of evaluating the semiconductor surface were the measurement of surface conductance in a finished MOS-FET device, then this would represent an intricate procedure in terms of analysis and time. The MOS capacitor, through its voltage-dependent capacitance, provides a convenient and simple means to examine the semiconductor surface. With the use of this instrument, a particular set of fabrication steps that produce the desirable properties of Q,, may be selected for the MOS-FET structure.

218

MARVIN H. WHITE

The nature of the Q,, associated with thermally oxidized silicon surfaces has received considerable attention by many workers.23 In the early work regarding the properties of semiconductor surfaces, these states were The “fast” generally interpreted in terms o ffast or slow surface states are electronic states within the forbidden gap of the semiconductor which are located at the surface and, hence, are in good electrical contact with the bulk semiconductor. For clean germanium and silicon surfaces, their density has been found to be of the order of the atomic surface density. For the thermally oxidized silicon s~rface,’~ their density has been found’ to be less than 5 x 10”/cm2, which results in the low surface recombination velocity observed on passivated silicon devices.24The slow surface states, in the historical sense, were associated with ion migration on semiconductor surfaces covered by thin oxides (e.g., less than loohi). With the advent of integrated-circuit technology and relatively thick SiO, layers, the term interface states has been associated with fast states. Ionic space charge within the SiO, and near the Si-SiO, interface26 has been observed. The oxide charge Q,, which will be discussed in Section 8, arises from the presence of such mobile ions as sodium and hydrogen or from exposure to ionizing radiation. These charges within the oxide have been found to be positive in nature, which induces a negative charge into the silicon surface. Thus, there is a tendency of thermally oxidized silicon surfaces to become n-type. The oxide charge Q, is in poor electrical contact with the bulk semiconductor. In addition to the oxide charge just described, there is a residual positive and it is surface-state charge Q,, within 200 A of the Si-SiO, interface26927 believed to be associated with excess silicon in the oxide that is ionic.2s929 In the discussions to follow the effective surface state will be treated as an entity located at the Si-SO, interface as shown in Fig. 5; however, at the end of this section a discussion will entail the separation of charge in the E. S . Schlegal, IEEE Trans. Electron Devices ED-14, 728 (1967). This is a comprehensive bibliography of more than 550 papers in the field of metal-insulator-semiconductor theory and technology. 23aA.Many, Y.Goldstein, and N. B. Grover, “Semiconductor Surfaces.” North-Holland Publ., Amsterdam, 1965. 24 M. M. Atalla, A. R . Bray, and R. Lindner, Bell Syst. Tech. J . 38, 749 (1959). 2 5 A. S. Groveand D. J. Fitzgerald, Solid Sfare Elerrron. 9,783 (1966). 2 6 B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow, J . Electrochem. Soc. 114,266(1967). 2 7 E. H. Snow, A. S. Grove, B. E. Deal, and C. T. Sah, J . Appl. Phys. 36, 1664 (1965). A. G. Revesz, IEEE Trans. Electron Devices ED-12, 97 (1965). 29 R. P. Donovan, Oxidation, Integrated Silicon Device Technology Ser. 7 Research Triangle Inst., Durham, N.C. Rep. ASD-TDR-63-316, DDC-AD-618-704, 1965. Presents a comprehensive review of silicon oxidation studies prior to 1965.This information is now available in R. M. Burger and R. P. Donovan. “Fundamentals of Silicon Integrated Device Technology,” Vol. I. Prentice-Hall, Englewood Cliffs, New Jersey, 1967. z3

4. MOS TRANSISTORS

219

Al-Si0,-Si system.29a Figure 6a29billustrates the various charges that may exist in the Al-SiO,-Si system. Thus, Q,, may consist of different charges and the assumed distribution at the Si-SiO, interface is for mathematical convenience.

0

+

+

0

+

0 +

Y

A

0

s102

+ A "

A

v

v

A,,

n- T YPE SEMICONDUCTOR

A

V

si

0-

FIG.6a. Classification of states and charges in the Al-SiO Si system. Interface states : .--slow. Oxide charge: @ -alkali ions, M -mobile ions, +-ionized traps, A-fixed oxide charge. (After White et ~ 1 . ~ ~ ~ )

x -fast,

In order to analyze the effectof various fabrication processes on the silicon surface, using the MOS capacitor method, it is necessary to standardize the preparation of the MOS capacitor. There are many factors to consider in the preparation and Table I is an attempt to list important categories. The discussion to follow is based upon the fabrication of enhancement-mode MOS-FET devices : The resistivity of the starting material (i.e., the semiconductor) is a major factor in the determination of the threshold voltage29c V, for a p-type semiconductor (n-channel MOS-FET) because of the positive 2g"Fora model of the Si-SiO, system, see Fig. 28. 29bM,H. White, F. C. Blaha, and D. S. Herman, NBS Symp. Silicon Deuice Processing, Gaithersburg, Maryland, June 1970. ASTM Committee F-1 and NBS in Nat. Bur. Stand. Spec. Publ. 337, p. 337. U S . Gov. Printing Office, Washington, D.C., 1971. "'See Fig. 3 and Eq. (23).

220

MARVIN H . WHITE

TABLE I

MOS Consideration 1. Oxygen vacancies 2. Chemical cleaning of silicon surface 3. Bulk silicon properties

4. Hydroxyl-ion effects 5. Sodium-ion effects 6. Interface states 7. Thermal stress at Si-SiO, interface 8. Bulk dopant segregation at Si-SiO, interface 9. Metal (AltSiO, interface

FABRICATION

CONSIDERATIONS Procedure

Bake in dry N, (i.e., liquid N, source) at 1100°C for 60 min to reduce the “state of charge” Hot H,SO, bathsfollowedbya 10-secdipindilute HFsolution; final post hot water soak to remove detrimental effects of fluoride ion on silicon surface Epitaxial surface formed at 1200°C using gaseous impurity source on ( I 11) crystalline orientation n-type surface using PH, with 1.0-3.0 ohm-cm resistivity; p-type surface using B2Hh with 0.24.5 ohm-cm resistivity Oxide grown using dry 0, followed by dry N, anneal ;evaporation system uses liquid N, “cold trap”; minimization of sources of water vapor such as use of desicators Oxide grown in phosphorus deposition furnace and phosphorus glass used to ”getter” sodium ions within the oxide; also prevents external sodium contamination Hydrogen annealing at high temperatures reduces interface state density Preanneal and postanneal of gate oxide at 350 and 1000°C in dry N, Use of high temperature, 1100”C, and dry 0, to minimize “pile-up” and “depletion” at interface Use of “sintering” at 500°C in dry N, to annihilate interface states caused by electron beam deposition

surface-state charge density Q,, normally found in thermally oxidized silicon surfaces. The variation in resistivity from device to device may be minimized by the use of epitaxially grown silicon substrates. Furthermore, the use of epitaxial surfaces offers the advantage of obtaining a silicon surface untouched by laboratory chemicals, such that the effects of these chemicals on the surface can be investigated. Since the early studies on MOS surfaces, the fabrication of complementary, enhancement-mode, MOS-FET devices has progressed from epitaxial, groove-etch and refill techniques on (111) silicon22 to the control of a P - boron diffusion into (100) ~ i l i c o n for ~~~-~ the substrate of the n-channel MOS-FET. This was due to the difficulty Z9dR.W. Ahrons, M. M. Mitchell, and J. R. Burns, l E E E Int. Solid State Circuits Con$ (ISSCC) Digest Tech. Papers 8,80 (1965).This work can also be found in the chapter by A. Karl Rapp, in “Field-Effect Transistors : Physics, Technology and Applications” (J. Wallmark and H. Johnson, eds.), p. 312. Prentice-Hall, Englewood Cliffs, New Jersey, 1966. 29eJ. R. Cricchi and M. H. White, Large Scale Complementary MOS Arrays. I E E E Int. Electron Device Meeting, Washington, D.C., October 1966 29fT.Klein, I E E E J . Solid State Circuits, SC-4. 122 (1969).

4. MOS TRANSISTORS

221

associated with uniform epitaxial refill of the groove-etched pockets and metalization over the refill step. For the p-type semiconductor, if an enhancement-mode MOS-FET is desired (i.e., V, > 0), then this requires an increase in bulk charge lQsl = IQ,] > ]QSJ while maintaining close control of the differential IQ,, - QsI. The threshold voltage for the n-type semiconductor, VT < 0, may be controlled entirely by the surface-state density Q,,, as the differential term is absent. The basic oxide preparation employed in the early studies on (111) epitaxial studies for the MOS capacitor fabrication (and eventually the MOS-FET structure) is illustrated in Fig. 7. An epitaxial substrate is the Mechanical Pol is h ing to 8 - 10 Mils

40-Min HCL Gas Etch at 12OO0C and. Epitoxtal Surface

-

Starting

1

------

*

42-Min 3 0Preheat - M i n Dry N2 Dry O2 a t 3500C-4500C . I , Phosphoros I IOOOC Growth Dep. Furnace of Oxide

r-Aluminum Evaporation

50008

I Photo Masking to Define Capacitor Pattern

Control Wafer Extracted at This Point

Material

I

Phosphoros Deposition Furnace

5 Min I O/O Oxygen Flow Std. Phosphoros Emitter Deposition

Slow Cool 5- Min 35OOC 450OC’ Dry N2

-

I

cv I.+ Measurements

-

Sintaring 5 - Min 550aC in Dry N 2

I

I I

160-Min Drv

I

N2 at 11000~ Annealing Operation

cv

*Measurements

FIG.7. Standard oxide preparation-capacitor fabrication flow diagram. (After White and Cricchi.ZZ)

222

MARVIN H. WHITE

starting surface and the entire oxide preparation is performed in a “phosphorus deposition furnace”29‘ at 1100°C. The initial growth of oxide at 1000°C prevents the epitaxial silicon surface from becoming “phosphorusdoped” from the wall of the diffusion tube. It is also necessary to prevent “auto-doping’’ which results when the substrate itself acts as a diffusion source due to the presence of high-concentration areas. The particular process sequence shown in Fig. 7 takes into account the following considerations: 1. The preanneal and postanneal operation minimizes the thermal stress at the Si-SiO, interface. 2. A temperature of 1100°C minimizes the redistribution3’ of impurity dopants in the bulk semiconductor near the Si-SiO, interface. This temperature is a compromise between control of junction depth in MOS-FET fabrication and impurity redistribution. 3. Annealing26*28.3’932 at the oxide growth temperatures in dry N , redistributes oxygen vacancies and reduces the number of surface states Q,, . 4. A phosphorus deposition which forms a phosphorus glass minimizes instability in the surface potential under temperature-bias ~ t r e s s i n g . ~ ~ - ~ ’ Since phosphine, PH3, is employed in the process, there is also H, due to decomposition. A limited amount of H, is desirable to reduce the interface state densit 5 a 5. The aluminum evaporation is performed immediately after the growth of the oxide, to minimize surface contamination. A sintering operation in dry N, is used to annihilate interface states caused by X-ray damage in the electron beam d e p ~ s i t i o n . ~ ~ ”

The capacitor pattern is defined using standard KMER photolithography

technique^:^ and a sintering operation is employed as indicated in Fig. 7.

In the early work, the aluminum was evaporated from a filament holder ; however, subsequent studies demonstrated that the ionic contamination from such filaments was in excess of ions/cm2. Electron beam evaporation technique^^^^,^^" have been found to give ionic contamination levels Z98Normally,the n + emitter of an n-p-n bipolar transistor receives its phosphorus deposition in this furnace. 30 B. E. Deal, A. S. Grove, E. H. Snow, and C. T. Sah, J . Electrochem. SOC. 112,308 (1965). 3’ M. Yamin, I E E E Trans. Electron Devices ED-l2,88 (1965). 32 D. R. Kerr, J. S. Logan, P. J. Burkhardt, and W. A. Pliskin, IBM J . Res. Develop. 8, 376(1964). 3 3 H. G. Carlson, G. A. Brown, C. R. Fuller. and J. Osborne, Phys. Failure Electron. 4, 390 ( 1966). 34 Y. Miura, S. Tanaka, Y. Matukura, and H. Osafune, J . Electrochem. Soc. 113,399 (1966). 34aS. A. Hoenig and R. A. Pope, Solid State Twhnol. 11, 53 (1968). 34bD. R. Collins and C. T. Sah, Appl. Phys. Lett. 8, 124 (1966). 35 E. Yon, W. H. KO, and A. B. Kuper, l E E E Truns. Electron Devices ED-13, 276 (1966). Balk, J . Electrochem. SOC.112. 69C (1965).

4.

223

MOS TRANSISTORS

below 10" ions/cm2. The electron beam system should consist of crucibles that are not hygroscopic and contain a low alkali concentration. Low temperature heat treatments at 500°C remove the electron beam damage due to X rays.34bThe basic oxide process of Fig. 7 and an oxide thickness of to, = 1000 8, yielded an experimental C-V curve with a separation of A V = V - V, = +3.4 V as shown in Fig. 8. With the use of Eq. (22), the surface state density35bpecan be calculated as N s s = QsS/q

=

( & 4 G X ) ( A v+

~ M s )

=

3.9 x 8.85 x 10-l4(3.4 - 1.0)/1.6 x

=

5.0 x 10"

x

states/cm2,

Experimental

N A = 4.0 x

0.6t -10

-8

-6

-4

-2

+2

+4

+6

+8

+I0

FIG.8. Comparison of theoretical and experimental C-V curves; to, = 10oO A, A V

=

+ 3.4 V.

35bTheinterface state density per unit energy p,, = -(l/qZ)aQ&$, can be obtained by the method of Terman' through a graphical differentiation of Q... "'The value of p,, can be determined by integration of the low-frequency C-V curve through a technique developed by C . N. Berglund, I E E E Trans. Electron. Devices ED-13,701 (1966). -'jdTheeffects of the oxide charge and interface states on the surface potential 4%can be separated by the Gray-Brown technique, which uses the incremental shift in the flat-band voltage V,, as the temperature of the MOS device is altered. P. V. Gray and D. M. Brown, Appl. Phys. Lett. 8, 31 (1966). "'The method of calculation indicated in Eq. (27) is to represent the entire charge distribution at the Si-SiO, interface as illustrated in Fig. 5. In practice, the distribution may be "locked" in the thin phosphosilicate glass over the SiO, gate oxide. The distribution of charge within the oxide may be written in the form vFB

dMS -

(1/K&O)

jr

xp(x)dx

3

where p ( x ) is the volume charge density (C/cm3).If the ionic contamination is the dominant charge and is located within a glass thickness t,, then, for a constant distribution, the flatband voltage becomes VFB = 4MS- (t,Qi,,/2K,co).

224

MARVIN H . WHITE

where the values of CbMS = - 1.0 V (0.5 ohm-cm p-type silicon) and CbMS = -0.3 V (3.0 ohm-cm n-type silicon) are used for the resistivities employed in MOS-FET f a b r i ~ a t i o n . ~ ~ A frequency-detection technique measures the capacitance-voltage (C-V) characteristics of the MOS structure. The test sample (i.e., MOS structure) is subjected to a variable dc voltage V, while employed as the branch of a variable oscillator as shown in Fig. 9. The signal from this oscillator is mixed I

oc

Variable

Fixed Oscillator

Bias

F1l L

I

a Meter

I

Square Rectifier Wave Generator r

DC -

I

F,

FI

- F2

F2

Mixer

1

- F2 I

Law - Pass

- Filter i

FIG.9. Schematic of MOS capacitance-voltage measurement. (After White and Cricchi.")

with a fixed or reference oscillator frequency to obtain the sum and difference frequencies. The difference frequency, F1-F2, is recovered from a low-pass filter and actuates a square-wave generator. The resultant output is rectified and amplified, where it is read as a capacitance on a calibrated meter The resistance R serves to isolate the supply voltage from the measuring circuit. The resultant C-V curve may be displayed using an X-Y recorder or individual points are read off the meter scale. The C-Vcurves discussed in this section were obtained at room temperature, in the dark,36bwith a measuring frequency of 100 KHz. B. E. Deal, E. H. Snow, and C. A. Mead,

J . Phys. Chem. Solids 27, 1873 (1966). For the aluminum/silicon system the metal-semiconductor work-function difference &S = -0.6 - & from Deal et al., although a value of 4MS = -0.40 0.13 - & is obtained from reported values of dM= 4.2 k 0.05 eV [J. C . Reviere, Proc. Phys. SOC. London 870, 676 (1957)land x = 4.05 k 0.08 eV [G. W. Gobeli and F. G . Allen, Phys. Rev. 127,150 (1962)l. 36aTheblock diagram in Fig. 9 may be realized by a Tektronix L-C meter No. 130. 36bTheeffect of illumination on the C-Y curve is to cause the capacitance in the heavy inversion region to approach the low-frequency value. The illumination decreases the minority carrier generation time in the inversion layer" and decreases the surface potential db[J. Grosvalet and C. Jund, IEEE Trans. Electron Devicrs ED-14, 777 (1967)l. 36

4.

MOS TRANSISTORS

225

The measurement of capacitance-voltage curves on p-type silicon substrates requires the termination of any inversion layer that may exist at V, = 0. If this inversion layer is not terminated, then the gate will be coupled to the surrounding area^^',^^ of the semiconductor substrate. When the capacitor is fabricated on MOS device wafers (i.e., an MOS capacitor and MOS-FET together on the same substrate), it has a diffused pf guard ring encircling the gate electrode ; however, on capacitor wafers, a guard-ring potential is required t o terminate the inversion layer. This is indicated in Fig. 10, where the guard ring is biased to form an accumulation region surrounding the gate electrode.

a

r p -Type Silicon

( a ) No Guard - Ring Potential

p-Type Silicon

7 \

Accumulation

(b)- 22.5 V Guard-Ring Potential

FIG.10. Measurement of p-substrate MOS capacitance versus voltage (cross-sectional view). (After White and Cricchi.22)

A particular case will be discussed to illustrate the use ofthe MOS capacitor in evaluating the fabrication processes for the MOS-FET. Discrepancies were initially found between C-V curves measured using the process of Fig. 7 and the actual MOS-FET characteristics. One of the major differences

’’ S. R. Hofstein, K. H. Zaininger, and G. Warfield, Proc. l E E E 52,971 (1964). 38

E. H. Nicollian and A. Goetzberger, I E E E Trans. Electron Dmices ED-12, 108 (1965)

226

MARVIN H. WHITE

between capacitor and device fabrication was the use of chemical cleaning procedures that “attacked” the device surface prior to gate oxidation. In the capacitor experiments, the silicon surface was not subjected to chemical cleaning before the growth of the gate oxide. In the MOS-FET procedure, the silicon surface was etched with a buffered HF acid solution followed by a hot H 2 S 0 , cleaning procedure. Experiments showed the HF acid was detrimental to the silicon surface and that, unless proper postcleaning methods were employed, the resulting number of surface states would be increased. Figure 11 indicates the various experiments that were conducted on a control wafer3*=in the preparation of the gate oxide for the capacitor studies. The results of the experiments shown in Fig. 11 indicate that HF is detrimental to the silicon surface and that postcleaning in hot, distilled

T

WCE + H 2 S O 4 + l l O O ° C Oxide a d - l l

WCE + H 2 S 0 4 + H 2 C R 0 4 + 1 1 0 0 ° C Oxide ad - Ila Run No 325

HF

+

H2S04 \

\

+ ll00”C Oaide ac - 9

HF

WCE

Control + H ~ S + O 1~ 2 0 0 0 ~ Oxide a d - 1 0 0

+ 1100°C Oxide ac - 80

W C E t HZS04 + HF + H o t Distilled H 2 0 Oxide ac - 79

0.6

.-

+ IIOO°C

4. MOS TRANSISTORS

227

H,O countered this effect.38bThe symbol WCE indicates an H F acid solution buffered with NH,F. It is seen that the MOS capacitor can be used as an experimental probe to study the semiconductor surface. In this particular example, a cleaning procedure was evaluated ; however, the method may be ion drift in the extended to the study of gas treatment^,^^.^"^^ impurity . o ~ i d e , ~ ’ , ~ ’ high-energy ,~~,~’ i r r a d i a t i ~ n , ~metal-semiconductor ~-~~ workfunction d i f f e r e n ~ e s . ~ ~etc. ,~~.’~ As mentioned previously in this section, the epitaxial process with the gate oxidation shown in Fig. 7 was developed during the period 1963-1965. In 1966, a low-temperature gate oxidation was developed to minimize the lateral diffusion in high density LSI arrays (see Sections 9 and 10).Figure 1 l a CHEMICALLY POLISHED (1001SI

OXIDATION Ski

- - - S T R I P OXIDE

IOOO’C DRV THERMAL 02 3 HR

+

HOT H z O CLEAN

-

1

CHELATING AGENT EDTA

HOT ‘ZS04

ELECTRON BEAM b ALUMINUM EVAPORATION 7kx

MISCIBLE ORGANIC SOLVENTS

PHOTOENGRAVING PROCESS

+

IOOO’C

DRY N Z ANNEAL IHR

1

P 2 0 5 Si 0 2 GLASS PHJSOURCE 950.C

7

SINTER

C-V AND

500.C

c-1

DRYNz 10-20MIN

MEASUREM E NTS

FIG.1 la. Low temperature gate oxidation with single-layer metalization for the Al-SO,-Si system. (After White er 38bG.B. Larrabee, K. G. Heinen, and S. A. Harell, J . Electrochem. Soc. 114, 867 (1967). These authors conclude that fluoride is retained by a chemical absorptive mechanism which is enhanced by oxidizing acid baths and reduced by hot water treatments. J9 G . Cherof, F. Fang, and D. P. Seraphim, I B M J . Res. Deuebp. 8, 416 (1964). 40 A. G . Revesz and K. H. Zaininger, I E E E Trans. Electron Deuices ED-13.246 (1966). 4 1 K. H. Zaininger and A. G. Revesz, Apyl. Phys. Lett. 7 , 179 (1965). 42 E. Kooi, Philips Res. Rep. 20, 578 (1965). 4 3 M. V. Whelan, Philips Res. Rep. 22, 289 (1967). 44 J. R. Szedon and R. M. Handy, Phys. Failure Electron. 5, 292 (1967). 4 5 D. R. Collins, D. K. Schroder, and C. T. Sah, Appl. Phys. Lett. 8,323 (1966). 4 h J. P. Mitchell and D. K. Wilson, Bell Syst. Tech. J . 46, 1 (1967). 47 K. H. Zaininger and A. G. Holmes-Siedle, RCA Reu. 28, 208 (1967). 4R E. H. Snow, A. S. Grove, and D. J. Fitzgerald, Proc. I E E E 55. 1168 (1967). “ R. Williams, Phys. Rev. 140, A569 (1965). 5 0 A. M. Goodman, J . Appl. Phys. 36, 141 1 (1965).

228

MARVIN H. WHITE

illustrates the low-temperature 1ooo"C gate oxidation and the use of a single metalization in contrast with the previous double metalization process. With the low ionic contamination obtained in electron-beam evaporation systems and KTFR (Kodak Thin Film Resist) the overall ionic contamination levels can be less than 10" ions/cm2. Improvements in the photoresist technology have been made, such as the use of benzenesulfonic acid to improve the adherence of photoresist to phosphosilicate glass surfaces through the removal of water by the formation of a hydrate. Other improvements in post cleaning have been realized through the use of ethylenediamine tetraacetic acid (EDTA) as a chelating agent which removes heavy-metal and alkaline-earth ions through the formation of stable intramolecular ring structures or chelate complexes. The charge distribution in the SiO, may be altered with an electric field and/or heat for a specified time interval. Undoped gate oxide samples are often employed to study the distribution of space-charge within the SO,. The distribution of space-charge p ( x ) in the SiO, may be divided into infinitesimal sheet charges located at a distance "x" from the AI-SiO, interface. Consideration of minimum energy for the capacitors formed by such a sheet charge leads to the expression2'

for the flat-band voltage VFB. Figure l l b indicates the redistribution of charge within the SiO, under a temperature-bias-stress (TBS) sequence. Step (a) shows the MOS system immediately after processing, with a distribution of charge toward the AI-SiO, interface. This distribution is due to the fact that the ionic charge occurs after the SiO, is formed over the Si surface. The first step in the TBS sequence is to move all of the mobile charge at room temperature (RT) to the Si-SiO, interface with the application of a field strength of approximately 2 x lo6 V/cm as shown in step (b). The field is reversed in step (c) and the difference between steps (c) and (b) represents the untrapped mobile (eg., hydronium ion) concentration in the SiO, . Step (d) illustrates the charge distribution after the application of an electric field of 2 x lo6 V/cm at an elevated temperature 200°C for 5 min. The sample is cooled to room temperature, under bias, and then the measurement is performed. Step (d) indicates all of the ionic charge is located near the Si-SiO, interface. Step (e) shows the effect of field reversal at room temperature and the difference between steps (d) and (e) represents the total mobile charge QM.A comparison of QM with the untrapped mobile charge in steps (b) and (c) will indicate the level of trapped mobile charge QMITwithin the SiO, . Experimentally, the trapped charge also exists at the Al-SiO, interface

4.

229

MOS TRANSISTORS

c/cins

PRECEDING CONDITIONS OF TEMPERATURE AND

Al ROOM TEMPERATURE

Si

g*

(d-20 VOLTS FOR 3 MIN

h7h97 /////////1

rn &-&f&-w M fuf%&&Y

ROOM TEMPERATURE

Id)+20 VOLTS FOR 5 MIN

2oo*c

;qf*

(el-20 VOLTS FOR 5 MIN ROOM TEMPERATURE

2oooc

/7%7%7% FIG 1 lb. Charge redistributlon under TBS in a nondoped SiO, MOS structure .-mobile charge QMT(trapped), 0-moblle charge QM, 0-alkall charge PA. A-fixed charge Q,, (After White et

since the separation of the initial curve in step (a) from the theoretical curve is approximately the metal-semiconductor work-function difference 4MS and fixed charge Q,, at the Si-SiO, interface. The fixed charge on (100)silicon surfaces is so small that, if it exists, it lies within the measurement uncertainty of the dMS. There is evidence that this intrinsic fixed charge is a result of

230

MARVIN H. WHITE

v,

(V)

FIG.1 lc. Sample TBS curves on an "unclean" MOS process sequence (run 1412A, wafer A-4);

fox = 1200 A. Curve 1 : Ci,, = 4.85 pF, +20 V at RT (room temperature) for 3 min; Curve 2: Cinn= 4.85 pF, - 20 V at RT for 3 rnin ; Curve 3 : Cins= 4.87 pF, 20 V at 200°C for 5 min ; Curve 4 : Ci,, = 4.89 pF, - 20 V at RT for 5 min ; Curve 5 : Ci,, = 4.85 pF, -20 V at 200°C for 5 min. (After White er a1.29b)

+

fluoride ion chemical adsorption on the silicon surface.34bThe Si-F bond is extremely tenacious and almost 70 %ionic, which would easily be polarized. The final step in the TBS sequence is the application of the electric field at 200°C for 5 min to move all of the ionic charge to the Al-SiO, interface. The difference between steps (e) and (f) is interpreted as the alkali ion contamination, whereas, the difference between step (f) and the theoretical C-V curve is the contribution of the &S and the intrinsic fixed charge. Figure l l c illustrates a TBS sequence applied to an Al-Si02-Si sample, with NJmobile > lo', ions/cm2, N,,(alkali) > 10l2 ions/cm2, and N,,(fixed) N 5 x 10" ions/cm2, to demonstrate the contamination present in an "unclean" process sequence. Figure 1Id illustrates the TBS sequence applied to a sample, with NJmobile) < 10" ions/cm2, N,,(alkali < 10" ions/cm2 and NJfixed) < 10" ions/cm2, to show the contamination levels observed in a "clean" process sequence. The preceding discussion was concerned with equilibrium C-V characteristics to determine the nature and distribution of charge within the SiO,. A

4. MOS TRANSISTORS

-5

-45

-4

-35

-3

-2.5

-2

-15

-05

-I

231

0

0.5

I

15

2

25

v, (V) FIG.1 Id. Sample TBS curves on a "clean" MOS process sequence; to, = 1100 A. Curve 1 : RT for 3 min at +20 V ; Curve 2 : RT for 3 rnin at -20 V ; Curve 3 ; 200"C, +20 V for 5 min; Curve 4 : RT for 5 min at - 2 0 V ; Curve 5 : 200"C, - 2 0 V for 5 min. (After White et

study of the AI-Si0,-Si with C-t or nonequilibrium measurements will yield information regarding the dynamics of minority carrier movement at the Si-SiO, interface and within the bulk depletion region of the Si. Figure l l e illustrates a C-t measurement obtained on a (100) orientation, n-type, 5 ohm-cm silicon MOS structure. The computerized data-reduction method of the Zerbst plot22byields a value of zg = 55 psec and an initial surface recombination velocity S(t = O f ) = 3.4 cm/sec. An approximation for the bulk-generation lifetime zg has been developed for negligible surface effects. If the decay of the C-t curve is linear with increasing time, then the capacitance may be represented by

c = C(t = O + ) + ([C,

-

C(t = 0')]/tF}t

Substitution of Eq. (27b) into Eq. (26c)and evaluation of the result at t yields the result, zg

=

(2niC,/INA - N,)CF){[CF -

c(t= Of)]/4C,)2

(27b) =

tF/2

(27c)

Eq. (27c) has been found to be accurate to within 10 % of the result obtained through computerized data-reduction techniques.

232

MARVIN H. WHITE

CF= I41 pF

I

1

I 1, = 196 sec

Y

0

0

20

40

60

80

M

.II I I I 100 I20 140 160 180 200 t [sec)

FIG.l l e . Pulsed capacitance-time ( C - r ) measurement of a MOS capacitor (run 1412A. wafer A 4 , device 1). Pulse range +20 to -20 V, T = 23”C, 20sec/in. (After White et ~ 1 . ’ ’ ~ )

111. MOS Transistors

4. DEVICE STRUCTURE The MOS structure when operating in the inversion region can be used to provide a voltage-controlled surface conductance. Figure 12 illustrates the geometric construction and electrical symbol of a linear-geometry, n-channel MOS-FET device. The gate electrode, gate oxide, and p-type substrate comprise the MOS sandwich, which was studied in the last section. The MOS-FET device provides ohmic contact to the thin n-type inversion layer under the gate electrode by means of the diffused n f regions shown in Fig. 12. The n’ regions are referred to as the “source” and “drain” electrodes, while the p-type semiconductor is called the “substrate electrode”. The discussion to follow and the subsequent derivation of the current-voltage characteristics of the MOS-FET will consider the “source” electrode electrically connected to the “substrate” electrode. The effect of a finite “substrate-to-source’’ potential will be considered in Section 9. Once the n-type inversion layer is formed under the metal gate electrode, it functions as a “channel” through which electrons flow from source to drain electrode. In operation, the source and substrate are electrically connected and the drain-to-substrate is reverse-biased with a positive

233

4. MOS TRANSISTORS WGate Lead Drain

G

q

+

bstrote Souke

Oxide

FIG.12. Geometric construction of an ti-channel MOS-FET and electrical symbol

potential V, at the drain electrode. The MOS-FET functions because of the ability of the transverse gate voltage V, to control the charge density in the channel region. If there exists a built-in n-channel at V, = 0 due to the presence of the surface state charge Q,,, then the device is called an n-channel depletion-mode MOS-FET. The origin of this name derives from the fact that, with the application of a negative gate voltage V, < 0, the electron charge density in the channel can be reduced o r depleted. This device may also operate in the enhancement mode, since an application of positive gate voltage V , > 0 serves to increase or enhance the electron charge density in the charnel. The n-channel depletion-mode MOS-FET’s require a gate voltage V, = -V, called the “pinch-off voltage” to reduce the channel current to zero. If the built-in channel is absent a t V, = 0, then a gate voltage V, = + V, is required to permit current to flow between source and drain electrodes. This voltage is called the “threshold voltage” and the structure is referred to as an n-channel enhancement-mode MOS-FET.”” The gate electrode of the MOS-FET controls the charge density in the thin channel region, which is shielded from the substrate by a depletion or space-charge region.50bThis is in contrast to the p-n junction FET, in which the conductance modulation is obtained through the voltage dependence of the channel thickness. A distinguishing feature between the MOS-FET and thep-n junction FET is that the channel occurs in the bulk semiconductor for the latter, while the MOS-FET has a surface channel. At low drain-tosource voltages, the MOS-FET is a voltage-controlled resistance operating in the triode region ; however, as the drain-to-source voltage or IR drop 50’Enhancement-mode MOS-FETs are sometimes called “normally OFF.” while depletionmode devices are referred to as “normally ON.” 50bIna practical structure, the channel thickness is of the order of kT/& or 10-100 A,while the maximum depletion-layer thickness is from 1000 A to 10,000 A.

234

MARVIN H . WHITE

along the channel increases, the effective gate voltage decreases, becoming lowest at the drain junction. This ZR drop will increase to a value such that the effective gate voltage near the drain junction is unable to form the inversion layer. The inversion layer becomes “pinched-off” and a so-called bottleneck forms at the drain junction. With the formation of this bottleneck, the drain-to-source current saturates, or reaches a limiting value. Thus, the device functions as a constant-current source and operates in the pentode region. There have been essentially three mechanisms proposed for the current saturation phenomena in field-effect devices : (i) velocity-limited opera ti or^,^',^^ (ii) space-charge limited ~ p e r a t i o n , (iii) ~ ~ ,a~ diffusion~ limited me~hanism.~’ Velocity-limited operation has been employed successfully in germanium p n junction FET’s to explain current saturation5’ and is a plausible explanation for the short-channel MOS-FET structure ; however, for the longchannel MOS-FET the channel field strength is below the critical field for saturation. The space-charge-limited approach to current saturation is applicable to MOS-FET’s with semi-insulating or lightly “doped” channels. For extrinsic channel structures, the saturation characteristics have been explained in terms of diffusion-limiting. Although the mobile-carrier concentration may be very small in the “pinch-off’ region, the gradient of the concentration is large. The carriers are injected into the channel by the source electrode and move along the channel by the drift mechanism. As they near the bottleneck, their contribution to the total current flow is determined by the carrier gradient, and the continuity of current is provided by the diffusion component. 5 . PHYSICAL DEVICE THEQRY

In this section, the current-voltage (Z-V) characteristics of the n-channel MOS-FET will be derived in a manner that permits correlation with the physical device parameters. An important consequence of the lateral surface current in the MOS-FET is that a two-dimensional analysis is required, in contrast with the conventional MOS capacitor theory of Section 2. While the MOS capacitor analysis was based on the constancy of the Fermi level (i.e.,the equilibrium theory), the presence of a lateral surface current requires Referring to Figs. 5 and 12, Eq. (20) the concept of a “quasi-Fermi J. Grosvalet, G . Motsh, and R. Tribes, Solid Stute Electron. 6, 65 (1963). C. D. Root and L. Vadasz, IEEE Trans. Electron Devices ED-11, 294 (1964). 53 G. T. Wright, Solid State Electron. 7 , 167 (1964). 5 4 J. A. Geursf Solid State Electron. 9, 129 (1966). 5 5 H. C. Pao and C. T. Sah, Solid State Electron. 9, 921 (1966). 51 52

4.

235

MOS TRANSISTORS

may be written as

where the tilde implies that these are nonequilibrium quantities which are functions of position along the channel. The electrostatic surface potential can be approximated’ by the expression

where 4,(inv) is obtained from the MOS capacitor theory of Section 2 and V ( y )= 4,(y) - 4F is the quasi Fermi potential difference between the electrons and the thermal equilibrium holes in the bulk semiconductor. Using Eqs. (3), (22), (28), and (29), the electron charge density in the channel region becomes

-

QAY) = -CJVG -

~ M S

4Jinv) - J‘(Y)~

-

Q,,

-

Q&).

(30)

An approximate form of the bulk charge QB(y)can be obtained by assuming that the major contribution comes from the ionized acceptor atoms in the depletion layer near the Using Eqs. (16), (18), and (29), the bulk charge may be written in the form

where VB is an effective bulk voltage, given as vB

=

[4qK,&0$F(NA- NdI1”/C0.

Insertion of Eq. (31) in Eq. (30) yields

QAY) = -Co[VG

-

~

M

S

4dinv)

-

~ ( Y )I

Qss

+ Q B ( 1 + [v(~)/”Fl}~”.

(33) The channel current can now be formulated in terms of the charge 0, in the inversion layer. The channel current can be written as I,

=

WJOXiJ(x, y) d x ,

(34)

where xi is the intrinsic point as shown in Fig. 5, and W is the width of the

MARVIN H. WHITE

236

channel region as shown in Fig. 12. The current density may be written J(x, Y ) = 4 ~ 5 +, qDn d n l d ~ = qpnn5, = -9pfln dVldY,

(35)

where p n is the mobility of carriers in the channel and n = n(x,y). The diffusion component of the total current is neglected; however, it becomes . ~ ~ total significant at the bottleneck and provides current ~ o n t i n u i t y The channel current may be written as (36)

6’ /IoXi

where use has been made of Eq. (14) and ji, is an effective mobility defined by the expression p , = p,n dx n dx . (37) Substitution of Eq. (33) into (36) and integrating along the channel length yields -1,

r

L

dY

(38)

Performing the integration in Eq. (38) and noting the drain current ID= - I , for the MOS-FET mode of ~ p e r a t i o n , we ~ ~ find " that the drain current is

The small-signal drain conductance is given as

is possible to have a lateral n - p n bipolar transistor action if the substrate-source junction is forward-biased. The leakage current of the drain-substrate junction is likewise neglected in the analysis.

4.

237

MOS TRANSISTORS

If the drain conductance is evaluated at VD = 0, then Eq. (40) becomes [letting 4,(inv) = 2&], gd(b =

0)

kco(w/L)(vG = -Dn(W/L)Qn

-

h)

(41)

3

where the voltage-controlled channel charge density, using Eq. (l), may be written as (42) Qn = - ( K o ~ d t o x ) ( V ~- h)Equation (42) reveals the operational aspect of the MOS-FET in the triode region. The drain current will saturate in the pentode region and the drainto-source saturation voltage VDs may be determined by setting g, = 0 in Eq. (40), yielding the relationship

Substitution of Eq. (43) into Eq. (39) yields the drain saturation current,

(44) Figures 13a and 13b illustrate the comparison of theory with experimental results obtained on p- and n-channel MOS-FET's, respectively. The triode and pentode regions are separated by the locus of all drain voltages satisfying Eq. (43). The bulk-charge contribution VBof Eq. (32) is a significant quantity in the pentode region and it can only be neglected in rare instances of extremely low doping levels and thin oxides. The small-signal transconductance in the pentode region can be obtained by differentiation of Eq. (39), =

"[

&C0-

L

1 - --(inv)

j

VDs,

(45)

where the dependence of Q,, on gate voltage V, has been neglected. This is valid so long as the fast interface states at the Si-SiO, interface cannot respond to the measuring frequency ; however, at low frequencies, the interface or surface state density (depending upon the fabrication processes used in MOS transistor construction) may depend upon gate voltage VGas shown in Fig. 14.55bThe values of Qss(VG) = C, AV and C,, may be obtained from a 5sbSincep,, = (l/q2)(3Qss/&&), the assumption of a constant Qss should be examined carefully for a given MOS-FET. Considerable variations in Q%$with gate voltage V, would imply that Q,, is to be regarded as an adjustable parameter with limited physical significance.

238

MARVIN H. WHITE p-Channel “Enhancement

VT =

- 4.lV

- Mode“ W/L

- FET

= 65 : I

iLp = 140

N D = 6 x 10” cm - 3 L = 7 . 8 ~

4.5

MOS

cm */V-sec

tox = l00oit

4.O 3.5

0

7’ 2.5 2.o I .5 I.o

0.5

0

0

0.5

1.0

1.5

2.0 2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

-vD ( V )

FIG. 13a. Drain current-voltage characteristics, theory (dots) and experiment (solid lines), fabrication on [I 1I] epitaxial silicon (p-channel MOS-FET).

frequency analysis of the short-circuit gate capacitance’ Cis at V, = 0. The low frequency C-V characteristics and Eq. (1) are used in this analysis and the density of interface states (states/cm2+V) is determined by the relationship p,, = C,,/q2. Figure 14 illustrates a peaked distribution of states near the valence-band edge for this particular p-channel MOS-FET. The variation of surface potential $,(inv) is rather small (see Fig. 6), and the entire effect of the bulk charge is contained in the saturation voltage V,, determined by Eq. (43).The effect of increasing the bulk charge for a specified gate voltage is to decrease the values of V,, and IDS. In the preceding analysis, the saturation drain conductance g , = 0 was a mathematical tool to define the pentode region. In a practical device, there remains a small but finite drain conductance in the saturation region. There have been two mechanisms proposed for this saturation drain con~ , channel~~ ductance : (i) drain-to-source-region electrostatic f e e d b a ~ k ,(ii) length m o d ~ l a t i o n . ~These ~ , ~ mechanisms are in parallel and the dominating 56

57

S. R. Hofstein and G. Warfield, IEEE Trans. Electron Devices ED-12, 129 (1965). V. G. K. Reddi and C. T. Sah, f E E E Truns. Electron Devices ED-12, 139 (1965).

4. MOS TRANSISTORS

239

n - Channel "Enhancement - Mode" MOS - FET = + 2.2 v N, = 8 x 1 0 ' s c r n - 3 L = 9.6 p

v,

-

5.0

4.5Triode Region

W/L

7"

=53:1

= 215 5m2/V-sec

to, = 1 0 0 0 A

Pentode Region '1

I

9

I .o

0.5 0

0

0.5

1.0 1.5 2.0 2.5

3.0 3.5 4.0 4.5

5.0 5.5 6.0

VD (V)

FIG.13b. Drain current-voltage characteristics, theory (dots) and experiment (solid lines), fabricated on [I 111 epitaxial silicon (n-channel MOS-FET).

effect will depend upon the particular MOS-FET. The electrostatic feedback is applicable to lightly doped or semi-insulating substrates. Under these conditions, the electric field of the drain electrode is electrostatically coupled to the channel. The charges within the channel are weakly controlled by the drain electrode, which acts as an inefficient gate electrode. When the substrate is sufficiently doped such that penetration of the drain field into the source region of the channel is negligible, then the channellength modulation becomes the controlling mechanism. As the drain voltage is increased beyond the saturation voltage VDs, the length of the pinch-off region widens, which causes an effective shrinkage in the channel. This effect is quite analogous to the Early effect57ain bipolar transistors. Figure 15 illustrates a model of the channel-length modulation in which the channel shrinkage can be approximated with an n + / p step junction57bat the drain M. Early, Proc. IRE 40, 1401 (1952). 57bThedepletion approximation neglects the contribution of carriers in the pinch-off region and is strictly applicable at high bulk dopings and low gate voltages. 57aJ.

240

MARVIN H. WHITE 5

4

2

FIG.14.(a)Thefrequency dependence of the short-circuit gate capacitance-voltage characteristics at VD = 0 for a thick oxide (6200 A) p-channel MOS transistor. (b) The interface (or chargeable) surface-state density plotted as a function of the energy at the interface with Ei labeled as the position of the intrinsic Ferrni level at the interface. (After Sah.*)

electrode. In analogy with Eq. (19),the shrinkage becomes

where V, - V,, is the effective voltage across the pinch-off region as

4. MOS TRANSISTORS

241

Metal Gate Electrode

Metallurgical Junction Depletion Region Boundary

p - Type Substrate

Substrate FIG.15 Channel-length modulation

indicated in Fig. 15. The drain current for V, > VDs can be expressed as L I,‘ = IDS(47) L - AL’ Upon substitution of Eq. (46) into Eq. (47), the saturation drain conductance becomes

where x,(max) is defined by Eq. (19) and I,, is given by Eq. (44). Inspection of Eq. (48) indicates that a decrease in channel length and bulk doping results in an increase in the saturation drain conductance. For the situation of small channel shrinkage in comparison to the total channel length, Eq. (48) becomes xd(max)’DS (49) gds = 2L[24,(VD - VDS)]”2’ 6.

SMALL-SIGNAL

8p6



The MOS-FET operation as a small-signal amplifier is based upon the control of the mobile charge density 0, in the surface channel. When the 58

59

6o 61

M. H. White and R. C . Gallagher, Proc. I E E E 53,314 (1965). N. G. Bechtel, unpublished communication, 1963. J. R. Hauser, IEEE Trans. Electron Druices ED-12,605 (1965) H. Johnson, Proc. I E E E 54, 1970 (1966).

242

MARVIN H. WHITE

device is operating in the pentode region with the drain junction "pinched off' as shown in Fig. 15, the transconductance g,, is determined by the ability of the gate voltage to control this charge density. The control mechanism is distributed in nature with the oxide and depletion-layer capacitances forming a distributed RC transmission line with the channel resistance as shown in Fig. 16(a). This transmission line may be replaced by a lumped

"q

T C g c

I

I

FIG.16. (a) Distributed nature of channel resistance with oxide and depletion-layer capacitances. (b) T-small signal equivalent "lumped" representation of part (a). (After White and Gallagher.58)

rcCc network in the form of a T-equivalent circuit as shown in Fig. lqb). Here, r, represents a lumped channel resistance and C, denotes the effective charge control element in the equivalent circuit.61aThe output of the model '"The distributive capacitance between the channel and substrate is neglected in the formulation of the charge control element. This is valid for the case of low bulk charge, which is expressed by the criterion o << [K,x,(max)/K,t&~,, where o, is defined by Eq. (59).

4.

243

MOS TRANSISTORS

is represented by a voltage-controlled current generator across a saturation drain resistance rp of the pinch-off region. The channel resistance and transconductance may be empirically related by rc = 4 ’ g m s

(50)

7

where 1< 1 can be determined experimentally for a particular MOS-FET at a specified operating point. In the special case of small bulk charge, L represents a fractional portion of the unpinched-off drain-to-source resistance of Eq. (41). In order to relate the T-equivalent circuit to the low-frequency parameters of Section 5, the n small-signal equivalent circuit is developeds8 neglecting internal feedback. The terminal relations indicated in Fig. 16(b) are written in admittance form for the intrinsic parameters as follows :

where s = j w and it has been assumed that rp >> r,. For frequencies o << l/rcCcrthe n-model may be equated to the low-frequency values as follows :

with the resulting amplification factor = gms/gds = gmTrp

(54)



Using Eq. (50),Eqs. (52) and (53) may be expressed in terms of the parameter ;L in the manner gms =

(l -

A)gmT?

gds

=

(l

- A)/rp.

(55)

The intrinsic y-parameters (i.e., those parameters pertaining to the physical device structure of the MOS-FET) may be written as

244

MARVIN H. WHITE

where 0, =

gmJ41 -

w,

(57)

is the intrinsic cutoff frequency of the MOS-FET. In the case of small bulk charge, the short-circuit gate to source capacitance discussed in connection with Fig. 14 is given as,*

c;,= ( y ; s / s ) ~ 6 0== oC,(1

-

1) = +cox,

(58)

where C,, = COWL [see Eq. (I)]. Using Eqs. (l), (43), (45), and (58), the intrinsic cutoff frequency for small bulk charge becomes 0, =

(59)

3P,(VG - VT)/2LZ/1,

illustrating the important parameters in obtaining high-frequency performance in a MOS-FET. The dependence on channel length is of interest in this respect. The high- and low-frequency equivalent circuits of the MOS-FET are illustrated in Fig. 17. The dotted lines indicate the extrinsic parameters such as the parasitic bulk resistances" and capacitances. For frequencies 0 << w, and neglecting the series resistance and internal feedback ( p >> l), the total y-parameters of the MOS-FET take the form Yis

=jOCis

Yfs

= gms

.vr\

2

- jocgd

=

-jwCg, ,

L'os = g d s

+ j d C g d + cds)

(60) ?

where Cisis the total short-circuit and the common source input capacitance is given by the approximate expression

ci, = +cox + c,, + c,,,

(61)

with Cox= COWL,and C, determined by Eq. (1). Examination of Fig. 17(b) indicates the striking resemblance between the MOS-FET and the vacuumtube pentode. In analogy with the latter, a figure of merit or gain-bandwidth product describing the performance of the MOS-FET as a small-signal amplifier in an iterative chain can be written as

+ Cds), Gain-bandwidth product = gms/(Cib

(62)

and it is seen that the gain-bandwidth product is degraded from the intrinsic cutoff frequency w, by the parasitic capacitance effects. Figure 18 illustrates the variation of the y-parameters with frequency for a lineargeometry device (see Fig. 12). 6'bThe parasitic bulk resistances include the erects of the offset geometry in depletion-mode structures and the series resistances.

4.

245

MOS TRANSISTORS

-L

1

O L

AS

(A) High Frequency MOS- F E T Equivalent Circuit

p

0

gms/gds =I;

2 cox

w < wc= 39,s

(8)

Low Frequency MOS - FET Equivalent Circuit

FIG.17. MOS-FET small-signal equivalent circuit : intrinsic parameters (solid lines). extrinsic parameters (dotted lines).

7.

sWITCHING

CHARACTERISTICS8’63-6

The transient response of a MOS-FET inverter circuit may be analyzed as shown in Fig. 19. It is assumed that the MOS-FET is initially in the off state as shown on the static characteristics by point a. With the application W. Fischer, Solid State Electron. 9, 71 (1966). T. J. O’Reilly, Solid Srate Electron. 8. 947 ( 1 965). b4 J. R. Burns, R C A Rev. 25, 627 (1964). 6 5 F. E. Capocaccia, Large Signal Transient Behavior of Metal-Oxide-Semiconductor Transistors (MOST), Int. Electron Device Meeting, Washington, D.C., October 1965. b6 J. T. Wallmark and H. Johnson, eds., “Field-Erect Transistors: Physics, Technology and Applications.” Prentice-Hall, Englewood Cliffs, New Jersey, 1966. 66aR.H. Crawford, “MOS-FET in Circuit Design.” McGraw-Hill, New York. 1967. bz

63

246

MARVIN H . WHITE

10 8 -

6 -

I

I

I

l

l

I

I

Measured y - Parameters .+~llr

O+y\ti

of a step voltage + V, to the gate of the MOS-FET, a channel will be induced between source and drain electrodes and an electron current will begin to flow between these electrodes. The voltage cannot instantaneously change across the capacitor plates66b and the operating point moves to point b. The time elapse between points a and b is the intrinsic delay time or channel time constant, given as td(ON)= l/w,

=

2L22/3ji,(VG - VT).

(63)

66bInthe following analysis, the gate-to-drain feedback capacitance and its “feedthrough effects” are neglected (i.e., C,, << CL).The feedthrough voltage or pedestal is calculated as CgdVC/(Cgd

+ CL).

4.

MOS TRANSISTORS

247

FIG.19. MOS-FET inverter operation (n-channel enhancement-mode MOS-FET neglecting feedback capacitance CgJ.

Equation (63) indicates the physical device parameters that determine the initial delay time of the MOS-FET. It is seen that, for a given set of device parameters, the delay time may be reduced by increasing the driving source voltage Vc. Once the operating point is at point 6, the MOS-FET drain voltage may be described by the differential equation CLd VDldt

= 1,

-

I,

(64)

and the load current is given by the static load line equation,

where V,, is the supply voltage and RL the static load resistor. The analysis is simplified for the pentode region, for, between points b and c, the MOS-FET behaves as a constant-current source ID = ,I given by Eqs. (43) and (44).

248

MARVIN H. WHITE

Combining Eqs. (64) and (65), the time elapse in the pentode region may be written as VDD d VD lP = RLCL V, - V,, + IDsR,

JVDs

where the approximation is valid if IDsR, > V,, - VDS. From point c, the operating point moves along the triode characteristic where the current I,,(V,) is a function of the drain voltage [see Eq. (39)]. The final operating point d is determined by the intersection of the static load line [Eq. (6511 and the triode characteristic [Eq. (39)l. The time elapse for the triode region may be written as

where the approximation66cassumes zero bulk charge and A , = g,,R, >> 1 in the active region of the device. The turn-on time to, is the summation of the various times as the operating point traverses the path from a to d, which may be written as to, = td(ON) -k t, t,. (68)

+

Let us consider a n example to illustrate the relative importance of each of the terms in Eq. (68).The MOS-FET inverter of Fig. 19 will have R, = 10 kR, C, = 5.0 pF, and the output characteristics of the n-channel MOS-FET of Fig. 13(b). Suppose the driving voltage is a step of V, = + 10 V ; then the various times may be calculated as follows : 1

2LZI

O,

3iin(VG- V,)

td(ON)= - =

- 2p.6 x

10-412

3(215)(10 - 2.2)

=

0.365 x

sec (435 MHz),

t, =

to,

c,(V,,

- VDs) -

1,s

=

4.0 x

=

td(ON)

5.0 x 10-'2(10 - 2.8) = 9.5 x 4.1 x 10-3

sec,

sec,

+ t, + t,

=

14

X

SeC.

6h'In essence, this approximation neglects the finite leakage current through the load resistor R , in comparison with the drain current. The zero-bulk-charge approximation implies that gms = gd(l/D = O).

4.

249

MOS TRANSISTORS

In this particular example, it is seen that the intrinsic time constant is a very small part of the turn-on time and the major limitation is the drain-tosource capacitance of the device. When the input voltage suddenly becomes zero, the channel will vanish and there will be an intrinsic delay time associated with the removal of stored charge in the channel. This delay time is on the order of the intrinsic delay time given by Eq. (63), and it represents a small portion of the turn-off time. The principal contribution is from the path e t o f a s shown in Fig. 19. The path from d to e represents the turn-off delay, which is negligibly small. Once the MOS-FET is “turned off’ at point e, the drain voltage will rise exponentially toward the supply voltage VDDas given by the expression VD

= VD,

- (VDD -

VoN)e-t’r,

(69)

where z = RLCL. If VDD > VoN; then the fall time can be defined by the conventional 10 % and 90 % points of the output to yield to,, = t ,

=

2.2RLCL.

(70)

For the previous example, the turn-off time becomes to,,

=

2.2 x lo4 x 5.0 x lo-’’

=

1.1 x lo-’

sec.

Thus, the important consequence of the preceding analysis is that the turn-on and turn-off times of the MOS-FET inverter are determined by the external circuitry rather than the device itself. Finally, the rise time of the MOS-FET is characterized by a constant-current operation, which results in a linear decrease in drain voltage with increasing time. In contrast, the fall time is determined by an exponentially decaying current, which gives an exponentially increasing drain voltage with increasing time. Figure 19 illustrates the output waveform of the MOS-FET inverter as a function of time. 8. FABRICATION AND STABILITY CONSIDERATIONS

The fabrication of a p-channel, enhancement-mode MOS-FET is shown in Fig. 20, with a corresponding fabrication flow diagram in Fig. 21. The process shown in these figures2’ is not unique, and it is only representative of a typical process sequence. For example, the method of gate oxidation may vary considerably both in the preparation of the silicon surface and in the formation of the oxide. The process shown utilizes a double aluminum metallization procedure, in which the first metallization and subsequent sintering protects the gate oxide against contamination. The second metalization provides the interconnection pattern and ohmic contact to the various regions. Figure l l a illustrates a gate oxidation process that employs only a single gate metalization and the substrate is (100) orientation, n-type

250

MARVIN H. WHITE

r-----l

n- Type Epitaxial Silicon

L

Growth of lnitiol Oxide

n

n

Contoct Mosk ond Metollizotion

I

Boron Source ond Droin Diffusion

L

I

Interconnection Mosk

tax

,-Aluminum

Gote Oxide Preporotion, Metallization and Sintering

Encapsulation

FIG.20. Fabrication of a p-channel enhancement-mode MOS-FET (linear geometry L is length, W is width).

silicon (nonepitaxial); however, for the purpose of explanation, the process shown in Figs. 20 and 21 will be used in the following discussion. Step (a) of Fig. 20 illustrates the initial growth of oxide on an n-type silicon surface, which is an epitaxial layer in this particular sequence. The epitaxial layer is generally 15-20pm (1 pm = cm) thick, and it has a resistivity in the range of 1-3 ohm-cm. The substrate material is typically 10 ohm-cm n- or p-type silicon which is 8-10 mils thick. After the growth of the oxide, as indicated in step (a),p + source and drain diffusion windows are opened in the oxide as shown in step b. The length L

Starting Material

Machonical Polishing

Gate Surfoce Preparation

Photoengroving (Gate Areas)

10% HF-15 sec Hat Water 20 min

Resist Stripped in

-

Oxidotion

- Dry

Sulfuric Acid 1

02

Preheat 350 - 4OO0C

4

10 min at 1 0 0 0 ° C

15min !

Aluminum Sinter 500OC 10 min o f N2 (C)

Photoengraving

( Contoct Windows 1

( a ) Etch AL (b) Etch 5 0 2

Bond T = 385 "C

c

(d

(f)

Seal T = 350% in N p

-

-

Aluminum Evaporation 5 k i Heated Substrate 250OC- 2 min

Aluminum Evaporation

5 k a Heated Substrate

(d 1

Scribe and Dice

,

Threshold Measurements

-

-

HCL Gas Etch

+

Epitoxial Loyer 1200oc

Source and Drain Diffusion (Prediffusion Cleon 1 Deposition and Drive in (b)

-

-

Oxidation

-

Dry 02

4 2 min ot llOO°C

1200~C Oxidotion ( 6 0 0 0 A 1

(O)

-

Photoengraving (Source ond Drain ) Resist Stripped in Sulfuric Acid

-

Redistribution

-

3 5 0 450OC

Photoengroving (Aluminum Contocts)

(el

C - V ond Threshold Measurements

Temp - Bias Stress

-

N2

c

( C )

Slow Cool - 5 min at 1000°C Dry N2 for 5 m i n a t

- Dry

60 min ot llOODC P

Phosphorus Gloss PHs 5 rnin llOO°C

C - V and Threshold Measurements (

El a)

i Aluminum Sinter 10 rnin at 5OO0C

3

E

(el

Stability Measurements

FIG.21. Fabrication flow diagram for MOS-FET structure. (After White and Cricchi.")

N

s

252

MARVIN H . WHITE

and width W determine the drain conductance &(VD = 0) at low drain voltages [see Eq. (4111, the transconductance g,, in the pentode region [see Eq. (45)], and the intrinsic cutoff frequency w , [see Eq. (59)J.The original length, designated by Lo at the top surface of the oxide, may be effectively reduced by thick oxides and deep diffusions such that66d L

=

Lo - 2(x0 + tb,),

(71)

where ?to is the junction depth of the source and drain regions and t i x the thickness of the masking oxide. Equation (71) expresses the fact that lateral side diffusion under the gate oxide and “undercutting” by the chemical etchant of the gate oxide reduces the effectivechannel length of the MOS-FET device, Step (c) indicates that the previous oxide has been completely removed, the surface given a preoxidation cleaning, and a uniform gate oxide grown according to the procedure indicated in Fig. 21. This procedure involves the deposition of a phosphorus-doped glass followed by an aluminum metallization to protect the oxide. The entire MOS sandwich receives a low-temperature sintering at 5W55O”C in a nitrogen flow stream. At this point, the procedure is identical to the standard oxide preparation discussed in connection with Fig. 7. Step (d) illustrates the [email protected]‘ of the source and drain contact areas and subsequent metallization. The interconnection pattern is applied as shown in step (e) with the bonding pads located over the thick initial oxide to avoid “shorting” to the substrate. The gate electrode, as shown in step ( e ) , overlaps the source and drain junctions to ensure a continuous inversion layer or channel between these two electrodes. The attachment of leads to the bonding pads and encapsulation is shown in step (f). The ohmic contact to the epitaxial layer is obtained with a eutectic gold bond between the starting material and the TO-5 header. The latter method is used if the substrate material and epitaxial layer are the same type ; however, with a p-type starting material, a separate n + ohmic contact diffusion is required to ensure adequate Ohmic contact to the n-type epitaxial layer. The device encapsulation as shown in this process sequence receives a “hermetic sealing” in a nitrogen atmosphere. It is often convenient in the analysis and testing of MOS-FET devices to have a MOS capacitor alongside the device (on the same substrate) to compare C-V and conductance measurements. Thus, the same TO-5 header contains one MOS capacitor and MOS-FET device. 66dEquation(71) assumes an etch factor of unity for the masking oxide, where the etch factor is the ratio of the lateral to downward etched distances. 6heIf the gate oxide is thin, then only one photoresist operation is sufficient to open aluminum and SiO, windows; however, with thick oxides, a double masking procedure may berequired.

4.

MOS TRANSISTORS

253

FIG.22. Experimental characteristics of p-channel MOST structure; 12 steps shown (40: 1 geometry-see Table 111).(After White and Cricchi.Z2)

FIG. 23. Experimental characteristics of an n-channel MOST structure; I2 steps shown (40: 1 geometry-see Table 111). (After White and Cricchi.‘’)

Figures 22 and 23 illustrate the characteristics of complementary p and n-type enhancement-mode MOS-FET’s fabricated with the process sequence shown in Fig. 21. These characteristics were obtained on an annular geometry with the dimensions shown in Table 11. The annular geometry shown in Fig. 24 has the drain electrode represented by the central circle, followed by the gate electrode, source electrode, and substrate electrode in a manner proceeding radially outward. The low-level switching characteristics of the p - and n-channel enhancement-mode MOS-FET’s are shown in Figs. 25 and 26, respectively. The experimental characteristics of these MOS-FET’s are indicated in Table 111, in which the surface state densities are comparable to those obtained from C-V curves. These devices were fabricated with (111) epitaxial silicon surfaces and a filament evaporation

254

MARVIN H. WHITE

TABLE I1 DIMENSIONS OF MOS-FET’s Channel length

WidthAength

Areas (less contact pads) (mil’)

Type

Ld(PL)

L(P)

WIL,

WIL

Gate

p n

12.8 12.8

7.8 9.6

40: I 40: I

65:l 53: I

20

18

40

-

-

-

Drain

Source

Prior to the etching of the masking oxide (5000 A) and the diffusion of the source and drain junctions. Junction depth of p-channel MOS-FET is 1.9 p while junction depth of n-channel MOS-FET is 1.1 p. These depths are measured after the growth of the gate oxide.

FIG.24. Annular geometry of MOST (channel length, 0.5 mils-see 200 x . (After White and Cricchi.”)

Table 111). Magnification

that contained a high level of ionic contamination. Table III(a) illustrates the experimental characteristics of identical device geometries that were fabricated in a clean metalization system with (100)silicon substrates. Figure 27 illustrates the C-V characteristics of MOS capacitors for the devices shown in Table 111 and the location of the threshold voltages. The surface state charge Qss,as mentioned previously in Sections 2 and 3, consists of interface states and oxide charge. The interface states N,, are the so-calledfast surface states and their number has been found to be less than 10” cm-’. The principal portion of Q,, is associated with mobile and immobile oxide charge. The immobile charge, as mentioned in Section 3,

4. MOS TRANSISTORS

255

FIG.25. P-channel MOST characteristics; 12 steps shown (40:1 geometry-see (After White and CricchiZZ)

Table 111).

FIG.26. N-channel MOST characteristics; 12 steps shown (40: 1 geometry-see (After White and Cricchi.22)

Table 111).

TABLE I11 EXPERIMENTAL CHARACTERISTICS OF MOS-FET’s FABRICATED ON ( 1 1 1 ) SILICON WITH UNCLEAN METALIZATION Channel type

Threshold voltage VT

Bulk doping level IN, - N,j (cm-7

P

-4.1 + 2.2

6.0 x 1015 8.0 x 1016

n

(V)

Surface state Density N,, = Q,,h

(ern-')

4.7 x 10” 4.3 x 10“

256

MARVIN H . WHITE

TABLE IIIA EXPERIMENTAL CHARACTERISTICS OF MOS-FET's FABRICATED ON (100) SILICON "CLEAN" METALIZATION Channel type

Bulk doping level N, - N ,

Threshold voltage V, (V)

1.0 x 1015 2.8 x 1016

+ 1.4

n

(cm-’)

(crn-7

- 2.4

P

Surface state density N,, = Q,,/q

2.2 x 10" 2.1 x 10"

LO--

+,

:+F=

--

1

V, (exp)

-8

-6

I

p-Channel En;;cpenf

-4

+s =24F;0.8 Nn= 8.0 x lola

n- Channel Enhoneement Mode

VT ( Thew )

-2

0.4

02

v = 4,-

8

+2

+4

+6

+8

FIG.27. C-V characteristics of MOS capacitors. The solid lines refer to the theoretical C-V curves, while the dashed lines are the measured C-V curves.

is believed to reside in ionized within 200 A of the Si-SiO, interface. Experiments have indicated that the immobilized surface state charge Qrs is always present in thermally oxidized silicon and its magnitude [l-2 x 10' charges/cm2 for (1 11) silicon and a factor of 2-3 lower for (100) silicon] is relatively independent of oxide thickness, conductivity type of silicon beneath the oxide, and resistivity of the silicon.25 This so-called intrinsic fixed charge may be moved under high electric field strengths.26 The oxide charge Q o ,which may be present in the oxide layer, is capable of

4. MOS TRANSISTORS

257

movement under the application of electric fields. Thus, the total surface state charge Q,, may be written as

neglecting the fast surface states.66‘A model of the Si-SiO, system is shown in Fig. 28, in which the fixed or immobile intrinsic charge and oxide charges are illustrated. Several mechanisms have been proposed for the oxide charge, such as alkali ions27,35(sodium), oxygen v a c a n c i e ~ ,protons, ~ ~ , ~ ~ 69-7 and polarization of the gate diele~tric.’~.’~ Experimental evidence2’*j5indicates quite strongly that the oxide charge can be traced to the contamination Fixed or Immobile Surface - State Charge

Si - SiOp lnterfoce

QIS

SiO2

+ + 8.0001 + + + 8.0001 +

+

Q 0000,

Inversion Layer ( Electrons) Qn Fixed Acceptor Impurity Atoms 0,

si P-type

Boundary of Depletion Layer

FIG.28. Model of the Si-SiOz system (depletion region and inversion layer induced by Qss

=

QE + QJ

hbfThepresence of fast surface states is manifest by a nonparallel shift of the experimental C-V curve from the theoretical C-V curve. 6 7 D. P. Seraphim, A. E. Brennemann, F. M. D’Heurle, and H. L. Friedmann, IBM J . Res. Develop. 8, 400 (1964). J. E. Thomas, Jr. and D. R. Young, IBM J . Rrs. Develop. 8, 368 (1964). 69 F. C . Collins, J . Electrochem. SOC.112, 786 (1965). ’ O S. R. Hofstein, IEEE Truns. Electron Det&.rs ED-13, 227 (1966). 7 1 S. R. Hofstein, IEEE Trans. Elecrroti Detiirrs ED-14, 749 (1968). 7 2 E. H. Snow and B. E. Deal, J . Elrctrochem. Sor. 113, 263 (1966). ’3 E. H. Snow and M. E. Dumesnil, J . Appl. Phys. 37, 2123 (1966).

‘*

258

MARVIN H. WHITE

of the system with sodium. The application of temperature-bias stressing to the MOS system can redistribute the mobile ions within the oxide, as shown in Fig. l l b . For example, if a positive bias is applied for several minutes at 100°C, then the mobile ions will accumulate at the Si-SiO, interface, resulting in a shift in the C-V curve and corresponding shift in the threshold voltage. This is shown in Fig. 29 for a p-type silicon semiconductor or n-channel MOS-FET. Investigations into the redistribution3 1-3 of sodium in SiO, using a phosphorus-doped thermal oxide have shown that phosphorus glass effectively "getters" any sodium that is in the undoped oxide and that the phosphorus glass also inhibits the migration of sodium ions in the gate oxide structure under field strengths of 2 x lo6 V/cm. Excessive use of the phosphorus glass leads to a polarization of the gate d i e l e ~ t r i c . Figure ~ ~ . ~ ~21 indicates the use of a phosphorus glass for MOS-

I I

I

C-V

I

I

SiO,

,-SiOp

Before Temp

\Theoretical Curve

- Bias Stress

After Temp -Bias Stress

Tronsfer Characteristic of n - Channel MOS- F E T

1

-'T

b

+V i a

FIG.29. Instability of threshold voltage VT resulting from temperature-bias stressing, which shifts the oxide charge.

4. MOS TRANSISTORS

259

FET device stabilization. With the use of phosphorus glass, the capacitor and device characteristics will be invariant under temperature-bias stressing, remaining at curve a in Fig. 29. Figure 30 illustrates the “gettering action” of the phosphorus-silicate glass with a segregation of sodium into this P,O,-SiO, layer. The sodium is effectively trapped in this layer and is not available to drift across the SiO, layer. Experimental measurements as shown in Fig. 30 indicate a three order-of-magnitude differential between the sodium in the phosphorus glass and the sodium in the SiO, layer. The migration of ionic charge may be inhibited with several dielectric systems : e.g., (1) P,O,.SiO,/SiO,, (2) Si3N4/Si0,, and (3) A1,O,/SiO2. Phosphosilicate glass (PzO,~SiO,)was the first mixed dielectric system discussed3’ with regard to surface stabilization in silicon integrated circuit technology. Next, the Si3N,/Si0, system was introd~ced’~” with the Si3N4 as a protective insulator for the SiO,. Other features of this mixed dielectric system have been discovered such as the ability to store charge at the interface of the two d i e l e c t r i ~ s . ’The ~ ~ Al,03/Si0, also provides passivation for the SiO, 7 3 c ; however, this mixed dielectric system is the least developed of those previously mentioned. The cross section of a complementary MOS-FET circuit is shown in Fig. 30a. The substrate for the p-channel MOS-FET is (100) orientation,

-Si

I I

I

0

0.1 0.2 0.3 0.4 0.5 0.6 Distance from Air Interface ( p )

-I

0.7

FIG.30. The effect of a P,O,-rich layer on the sodium concentration distribution within the oxide. (After Yon et aL3,)

73aJ.V. Dalton, J . Electrochem. Soc. 113, 1650 (1966). 73bT.L. Chu, J. R. Szedon, and C . H. Lee, Solid Stute Electron. 10. 897 (1967). ’3cG.T. Cheney, R. M. Jacobs, H. W. Korb, H. E. Nigh, and J. Stack, IEEE I n t . Electron DKV. Meeting, Washington, D.C., 1967.

260

MARVIN H. WHITE

FIG.30a. Cross section of a complementary MOS (CMOS) circuit

4-8ohm-cm n-type silicon. The substrate for the n-channel MOS-FET is obtained by means of a low concentration, p - boron diffusion to give a nominal surface concentration of 3 x 10l6cm3. This corresponds to a sheet resistance of 80&1000 ohms per square at a junction depth of 11-13 p. It is difficult to control the uniformity of the p - boron diffusion in CMOS circuits. To prevent parasitic channel formation in CMOS circuits, a combination of thick field oxides and channel "stops" are employed in the design. The field oxide is the oxide over which the interconnect metalization travels and this oxide is normally 15-18 k A in thickness. The field oxide is formed by a low temperature SiO, (phosphorus doped) glass such as the pyrolysis of silane (SiH,) over a thermal oxide. Channel stops are n+ diffusions into n-type substrates and p + diffusions into p - substrates in a manner such as to increase the parasitic threshold voltage under an interconnect metalization. Figure 30a illustrates the use of p + channel stops to prevent parasitic channel formation in the n-channel MOS-FET. Section 10 discusses the operation of CMOS circuits.

IV. MOS Transistor Circuits 9. P-CHANNEL MOS-FET CIRCUITS

The MOS-FET device possesses two unique properties :voltage-controlled resistance and threshold voltage, and capacitive storage (temporary memory). In the development of the I-I/ characteristics of the MOS-FET (Section 5), the structure was analyzed as a three-terminal device with the substrate-to-source potential V,, taken as zero. In order to include the effect

4. MOS TRANSISTORS

261

the electrostatic surface potential

of the substrate-to-source is written as 4,(inv) = 2&

+ V,,.

(73)

The new effective bulk voltage may be written

where VB is the bulk voltage at V,, = 0 defined by Eq.(32).Thus, the result of a finite value for V,, is to modify the threshold voltage74ato the form

Figure 31 illustrates the variation of VT with substrate voltage V,, for an

I 6.0

-

VT

= VT

+ VB

[

I

( I +

Vsr ) 2

*4F

- I

]

4.0 -

n- Channel Enhancement- Mode MOS - FET

N, = 8.0

OL 0

I

0.2

I

0.4

I

I

I

0.6

0.8 V ,,

( Source

-

x 1 0c m~- 3 ~

I

I.o 1.2 Substrote Potential )

FIG.3 1. Variation of threshold voltage with substrate bias-xperiment (solid line).

I

1.4

I

1.6

(dots) and theory

A. S. Grove, “Physics and Technology of Semiconductor Devices.” Wiley, New York, 1967. This is an excellent textbook describing equilibrium and nonequilibrium conditions at a semiconductor surface. 74”Thevariation of threshold voltage V, with temperature has been studied for silicon structures for surface states d ~ m i n a n t ’and ~ for surface potential d ~ r n i n a n t . ’ ~ 7 5 F. P. Heiman and H. S . Miller, f E E E Trans. Electron Deuices ED-12, 142 (1965). 7 6 L. Vadasz and A. S. Grove, l E E E Trrrns. Electron Devices ED-13, 863 (1966). ’4

I

1.8

262

MARVIN H. WHITE

n-channel MOS-FET.76a The drain conductance is thus modified in the manner Ed( v, = 0) = &C0( W / L ) (v, - Q . (76) The p-channel MOS-FET is used as a voltage-controlled r e s i ~ t o r ~ ~ ~ , ” - ~ ~ in order to provide the load resistor R, of the basic inverter circuit of Fig. 19. This “all p-channel” enhancement-mode MOS-FET inverter is shown in Fig. 32 with the substrate returned to ground potential to ensure adequate isolation between all diffused junctions in the integrated circuit. Figure 32 illustrates a p-channel MOS-FET T, operating as a driller transistor, while Tl serves as the load resistor. A gate voltage V,, more negative than V,, by would allow the channel to continuously connect the source and drain VDD electrodes of TI. When the driver (T,) is OFF, the output voltage V, with very little voltage drop across the load ( Tl). The effective threshold voltage pTof Tl is determined by Eq. (75)using Ks = V, = VDD. The effective load resistance of Tl may then be calculated from Eq. (76). When the driver is ON, the output voltage V, = - V,, may be made quite small through the design of a low-conductance Tl MOS-FET and high-conductance T, MOS-FET. It is also possible to connect the gate of Tl to its drain (i.e., V,, = V,,), in which case the output voltage swing is reduced by The MOS-FET inverter of Fig. 32 is the basic building block of integrated digital MOS-FET circuits. The p-channel enhancement-mode MOS-FET serves in three different capacities” in integrated digital MOS-FET circuits : driver, load, and coupling switch. The driver and load applications have been discussed in connection with the MOS-FET inverter of Fig. 32. Figure 33 illustrates the use of the p-channel MOS-FET as a driver, load, and coupling switch in a 2-phase dynamic shift register. This circuit is an example of the chargestorage properties of the MOS-FET. The gate electrode of the MOS-FET is extremely sensitive to charge accumulation and this provides a dynamic capacitive storage or temporary “memory” in switching circuits. The limitation to this memory time is determined by the charge retention of the gate capacitance shunted by an OFF MOS-FET.A bit time is the time interval between successive clock pulses of clock “A.” In the clock “A,” pulse

vT

5.

76”AlthoughFig. 31 illustrates an enhancement-mode device, it is possible to have a depletionmode device (V, < 0) become an enhancement-mode device ( pT > 0 )under the application of sufficient substrate bias. ” L. Vadasi IEEE Trans. Electron Devices ED-13, 459 (1966). ’* H. C. Lin, H. W. Van Beek, J. C. Tsai. and P. S. Shiota, Proc. N a t . Electron. Con5 XXI,96 (1965). ’ 9 R. D. Lohman, Semicond. Producrs Solid Sruie Tech. 9.23 (1966). n o H. Z . Bogert, Jr., Semicond. Products Solid Stair Tech. 9, 30 (1966). R. M. Warner, Jr., IEEE Spectrum 4, 50 (1967).

4. MOS TRANSISTORS

263

+TVD T p (Driver )

-vG

I

(a)

-VD D

-

VD

(b)

FIG.32. (a) Schematic of all-p-channel enhancement-mode MOS-FET inverter. (b) Characteristics of (high-g,) T2.

duration interval T3 is turned ON and the information present at the gate of TI is inverted and transferred to the gate capacitance C of T5. When clock “A” is turned OFF, this turns T3 OFF and the gate of T, is decoupled from the drain of q . The information is thus stored or retained in a temporary memory at the gate of T5 limited by the capacitive discharge through the OFF MOS-FET T3 as indicated by the arrow in Fig. 33. If the clock “B” arrives prior t o any sufficient charge leakage, then the information is transferred to the output, which is the input to the next bit. Thus, the same information is present at the output, except that it is delayed by one bit from the input. Cascading n such stages permits the construction of an n-bit shift register. An important feature of the MOS-FET is the bilateral switching characteristic of T3, in which the source and drain of T3 interchange roles depending upon whether it is charging or discharging the capacitor.

264

MARVIN H. WHITE Clock “ A “

Clock “ B “

Coupling Switch

Driver

T6

I

output

-A-

-r+

Input

-r

-

I

Storage

- -=t

1 -

One Bit

Clock ”A“

1Clock



B“



I



I

!

t=-

Temporary Memory Time

I

FIG.33. One “bit” of a 2-phase “dynamic storage” shift register.

10. COMPLEMENTARY MOS-FET

CIRCUITS29d’e’64’79’Bo~Bz-~4

The basic complementary MOS-FET building block is the inverter shown in Fig. 34. In operation, the inverter has negligible standby power dissipation providing both MOS-FET’s are enhancement-mode devices. The extremely small standby power dissipation is a consequence of the fact that there is always an OFF MOS-FET in series with the supply voltage. The switching F. M. Wanlass and C. T. Sah, IEEE Int. Solid State Circuits Con$ (ISSCC) Digest Tech. Papers 6.32 (1963).This work can also be found in G. E. Moore, C. T. Sah, and F. M. Wanlass, “Micropower Electronics” (AGARDograph No. 77, E. Keonjian, ed.), p. 41. Pergamon 83

84

Press, Oxford and Macmillan, New York, 1964. A. H. Medwin and B. Zuk, Using MOS Transistors in Integrated Circuits, Electronic Design, Part 1.-November 23, 1964; Part 11-December 7, 1964. J. R. Burns, J. J. Gibson, A. Harel, K.C. Hu, and R. A. Powlus, IEEE Int. Solid State Circuits ConJ (ISSCC) Digest Tech. Papers 9, 1 I8 (1966).This work can also be found in J. R. Allison, F. P. Heiman, and J. R. Burns, IEEE J . Solid State Circuits SC-2, 208 (1967).

4. MOS TRANSISTORS

265

speed of complementary MOS-FET inverters is enhanced by the availability of discharge currents of both polarities. With the application of a positive input voltage VDD, the p-channel MOS-FET (TI) is turned O F F and the n-channel MOS-FET (T2)is ON. The situation is reversed as the input voltage drops to ground potential. The total power dissipation of the complementary MOS-FET inverter is the sum of the standby (P,) and transient (P,) power dissipations. For the case of a square-wave voltage excitation, the power dissipation becomes Pd

=

P,

+ C,V,”f,

(77)

where f is the frequency of the square wave. The standby power dissipation for enhancement-mode devices can be attributed to reverse junction leakage A in a 3 mil2 planar-passivated currents, which are typically less than area. For example, consider the typical bulk generation lifetime zg = 20 sec

i

vDD

(a)

Schematic

n-Channel On

(on) (off

1

TI ( o f f ) TZ (on)

VDD VD

“D

( b ) Characteristics FIG.34. Complementary MOS-FET inverter.

266

MARVIN H . WHITE

800

$ 400 0)

3

t

200 0

0

1.0

2.o

3.0 P

(mW)

4.0

5.0

6.0

FIG.35. Theoretical (solid line) and experimental (dots) power dissipation versus frequency for a complementary MOS-FET inverter. Digit/Sense

1

Line

Reod

'

Write

tv

FIG.36. Complementary MOS-FET nondestructive readout (NDRO) memory cell. (After Burns et

4. MOS TRANSISTORS

267

FIG.37. Enlargement of a 16-bit section (28 mils x 40 mils) of a 288-bit complementary MOS-FET memory array with a density of 115,000 MOS-FET'S per square inch. (After Cricchi et af.85)

J. R. Cricchi E. Lancaster, and G. Strull, IEEE Trans. Aerosp. Electron. Syst. (Suppl.)AES 3, 677 (1967).

268

MARVIN H. WHITE

obtained in CMOS devices. The generation current may be calculated as74 Isen= (qniq/T,)Aj

1 X lo-”

A

(78)

where Wj and Aj are the junction depletion layer width and area, respectively. The low resistivity required to obtain n-channel enhancement-mode devices (V, > 0) is a factor in limiting the switching speed of the complementary MOS-FET inverter. This is due to the increased drain-to-source capacitance C,, of the n-channel MOS-FET as compared to the p-channel MOS-FET of the same geometry. Figure 35 illustrates the experimental and theoretical results obtained on a complementary MOS-FET inverter circuit. A particular area where complementary MOS-FET devices find a unique application is in large-scale integration memory arrays-in particular, those arrays in which the storage period may vary from many hours to times as small as a fraction of a microsecond. The complementary MOS-FET arrays offer high performance with a standby power dissipation of less than 1 nW per memory cell and a low switching or transient power dissipation due to the small load capacitance obtained in integrated-circuit fabrication. A

FIG.38. CMOS 288-bit memory chip (200 mil x 190 mil) in a 40-pin kovar package. (After Cricchi et 01.’’)

4.

MOS TRANSISTORS

269

single “memory cell’ is shown in Fig. 36 which consists of two cascaded inverters, clocked input gates, and clocked feedback or “latch-on’’ gates. For writing information into the memory cell, the feedback loop is opened and input gates closed with WRITE = + V and WRITE = 0. When WRITE = 0 and WRITE = +I/, the input gates are opened and the feedback gates are closed such that the information is stored in the complementary flip-flop (i.e., the two cascaded inverters and closed feedback loop). The memory cell is read out by placing the READ line at + V and sensing the line current that flows in the DIGIT/SENSE line.84 Since this readout is accomplished with the input gates isolated from the DIGIT/SENSE line, the readout signals do not alter or destroy the cell information. The cell information can only be altered when new information is written into the memory. While the memory cell of Fig. 36 uses current sensing for readout, a voltage-type readout has been employed in which the level sensed is identical to the level stored in the memory.8s Figure 37 illustrates an enlargement of a 16-bit section of an integrated 16-word by 18-bit, nondestructivereadout (NDRO) memory which employs a voltage-type readout. The complete 288-bit CMOS memory chip (200 mil x 190 mil)85in a 40-pin kovar package is shown in Fig. 38.

List of Symbols Voltage gain, g,,RL Capacitance/unit area of MOS structure Effective charge control capacitance in “T” equivalent circuit Instantaneous depletion layer capacitance Kse,/xd Debye space-charge capacitance per unit area, K,&,/LU Drain-to-source capacitance Equilibrium capacitance in the heavy inversion region at high frequencies Flat-band capacitance per unit area K,&,/L,* Gate-to-drain capacitance Gate-to-source capacitance Total and intrinsic short-circuit, common source, input capacitances Load capacitance Oxide capacitance/unit area Oxide capacitance COWL Space-charge capacitance/unit area Surface-state capacitance/unit area Control voltage in “T” equivalent circuit Electron energy at the conduction band edge Equilibrium electron energy at the Fermi level Electron energy band gap, ( E , - Ev)/q Electron energy at the intrinsic Fermi level in the bulk and in the surface spacecharge region, respectively. Electron energy at the valence band edge Frequency, Hz Normalized electric field function referenced to intrinsic Fermi level

270

g ds

QD QG

Q,, Q.. 0"

MARVIN H. WHITE

Small-signal drain conductance in triode region Small-signal drain conductance in triode region at VD = 0 and substrate-tosource potential V,, = 0 Small-signal drain conductance in triode region with an applied substrate-tosource potential V,, Small-signal drain conductance in saturation or pentode region due to channel shrinkage Small-signal transconductance in saturation or pentode region (n-model) Small-signal transconductance in saturation or pentode region (T-model) Small-signal gate and drain currents Channel current Drain current Drain current in saturation or pentode region corrected for channel shrinkage Saturation drain current Load current Current density (A/cm*) in the channel region Boltzmann's constant Dielectric constant of the oxide and semiconductor, respectively Channel length and channel shrinkage, respectively Intrinsic Debye length Extrinsic Debye length Length of photoresist pattern on oxide prior to etching and sourcedrain diffusion Slope of the linear portion of the Zerbst plot Electron concentration in the semiconductor Equilibrium electron concentration in the semiconductor Intrinsic carrier concentration in the semiconductor Acceptor and donor concentrations, respectively, in the semiconductor Surface-state density, QJq. states/cm2 Fast interface state density (QJq statesicm') Hole concentration in the semiconductor Equilibrium hole concentration in the semiconductor Power dissipation Magnitude of the electronic charge, with positive sign for holes and negative sign for electrons Equilibrium and nonequilibrium portions, respectively, of semiconductor charge density (C/cm') due to ionized bulk impurities INA - ND( Debye space charge density, kTCD/q Charge density on metal field plate, C,V, Immobile surface-state charge density Equilibrium and nonequilibrium electron charge density in inversion layer, respectively Mobile oxide charge density Equilibrium and nonequilibrium net total charge in semiconductor, respectively;

Q, + Qe

=

Q,

Surface-state charge density Fast interface charge density Lumped channel resistance in Tequivalent circuit Saturation drain resistance in T equivalent circuit Parasitic source and drain resistances

4. MOS TRANSISTORS

271

Load resistor Complex frequency Surface recombination velocity (cm/sec) Turn-on intrinsic delay time Fall time Turn-on time, to, = td(ON)+ tT + 1, Turn-off time Thickness of gate oxide Thickness of masking oxide Turn-on triode and pentode region times, respectively Temperature, "K Normalized potential, q+/kT, referenced to intrinsic Fermi level Normalized Fermi potential, qdF/kT Normalized surface potential, q&/kT Small signal gate and drain voltages, respectively Theoretical gate voltage with g5MS= Q,, = 0 Bulk voltage in equilibrium (Ks = 0) and nonequilibrium (Lis # 0). respectively Drain voltage Drain supply voltage Drain saturation voltage Flat-band gate voltage measured at 4, = 0 Voltage applied to metal gate electrode referenced to semiconductor Voltage applied to gate of load resistor with reference to grounded substrate Oxide voltage in equilibrium and nonequilibrium, respectively Oxide voltage in equilibrium at Vb = 0 On voltage of MOS-FET inverter Substrate-to-source potential Threshold voltage in equilibrium (V,, = 0) and nonequilibrium (V,, # 0) measured at ds = 2&. respectively Quasi Fermi potential difference 4"(y) - 4F along channel Voltage separation V - VGbetween theoretical and experimental C-vcharacteristics Width of channel region Effective width of the depletion region in equilibrium and nonequilibrium, respectively maximum effective width of depletion region in equilibrium evaluated at

4 s = ?dF

Intrinsic width of space-charge region di = dF Source and drain junction depth Small-signal, common-source, total admittance y-parameters Small-signal, common-source, intrinsic admittance y-parameters GREEKLETTERS EO

1

P

Pn ii.3

lip

Permittivity of free space, 8.859 x 10- l4 F/cm Experimental parameter related to T equivalent circuit Amplification factor of MOS-FET Electron mobility Average electron and hole mobility, respectively

272

P P S ,

7

d,

MARVIN H . WHITE

Longitudinal electric field in channel region Electric field at semiconductor surface Net charge density within the semiconductor Density of interface states C,,/q2 states/cmz-eV Load time constant Electrostatic potential with respect to electrostatic potential in the bulk semiconductor, = ( E , - E J q Surface potential relative to intrinsic Fermi level Surface potential with respect to intrinsic Fermi level at Yc = 0 Fermi potential, +F = ( E , - E F ) / q Metal work function Metal-semiconductor work-function difference Surface potential in inversion region, +s > +F Semiconductor electron affinity Intrinsic cutoff frequency Experimental parameter related to “T” equivalent circuit Load time constant R,C, Bulk generation lifetime

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