High-energy ion implantation for electrical isolation of microelectronic devices

High-energy ion implantation for electrical isolation of microelectronic devices

Nuclear Instruments and Methods in Physics Research B 89 (1994) 290-297 North-Holland High-energy ion implantation of microelectronic devices NOMB ...

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Nuclear Instruments and Methods in Physics Research B 89 (1994) 290-297 North-Holland

High-energy ion implantation of microelectronic devices

NOMB

Beam Interactions with Yaterlals & Atoms

for electrical isolation

M.C. Ridgway, S.L. Ellingboe, R.G. Elliman, J.S. Williams Department of Electronic Materials Engineering, Research School of Physical Sciences and Engineering, Australian National University, Canberra. Australia

Recent developments in the use of high-energy ion implantation for electrical isolation of both group IV (Si) and III-V (InP, GaAsl devices are presented. For Si devices, dielectric isolation can be achieved with the fabrication of a buried SiO, layer by high-dose ( - 10’s/cm2), high-energy (1 MeV) O-ion implantation. With MeV implant energies, implant temperatures ( - 150°C) can be significantly reduced compared to those required (- 55OT) in a conventional, low-energy (150-200 keV) SIMOX fabrication process and consequently, striking differences in post-anneal defect structures are apparent. Also, novel methodologies (high-energy 0 and Si co-implantation) for achieving low defect density SIMOX material are described. For III-V devices, electrical isolation can be accomplished with the production of implantation-induced disorder wherein the resulting deep-levels effectively trap charge carriers. Conventional, low-energy (100-200 keV) implant isolation schemes necessitate multiple-energy, multiple-ion implant sequences. In the present report, a single, low-dose ( - 10’3/cm2), high-energy (5 MeV) O-ion implant is shown to result in comparable electrical isolation with significant processing simplification.

1. Introduction Device/ substrate and device/ device parasitic effects degrade the operation of microelectronic devices. Consequently, device-specific electrical isolation schemes require constant development and/or refine-

ment with changes in both device dimensions and elemental constituents. For the present report, electrical isolation schemes based on high-energy (MeV) Oion implantation are reviewed for both group IV (Si) and III-V (InP, GaAs) materials. Though both schemes derive from established low-energy (keV) technologies, high-energy implant isolation is shown to offer both processing flexibility and simplification and also, insight into the materials-specific phenomena responsible for electrical isolation. For Si devices, complete dielectric isolation is achievable with the SIMOX process (Separation by IMplantation of Oxygen) wherein a buried SiO, layer is formed by low-energy (1.50-200 keV), highdose (- 1.8 x 101*/cm2), high-temperature (- 550°C) O-ion implantation [l]. Following high-temperature (- 1320°C) annealing to reduce the concentration of both defects and SiO, precipitates, a device-quality, Si over-layer of thickness - 0.2 km is separated from the bulk Si substrate by a buried, insulating SiO, layer of thickness - 0.4 pm. In CMOS devices fabricated in SIMOX substrates, parasitic capacitance between the source/ drain and substrate is decreased, device/ device latch-up is eliminated and radiation tolerance is 0168-583X/94/$07.00

increased. Such advantages have prompted commercial production and consequently, SIMOX substrates are now available from several suppliers. Fig. 1 compares theoretical vacancy distributions for O-ion implantation at 0.2 and 1.0 MeV to doses of 1.45 X 1018 and 2.15 x 10i8/cm2, respectively. (Such plots, indicative of the athermal ion-induced disorder production, are proportional to the rate of nuclear energy deposition or equivalently, the energy deposited into atomic displacements.) With an implant energy of 200 keV, high-temperature ( - 550°C) implantation is necessary to inhibit complete amorphization of the Si over-layer. Conversely, significantly lower implantation temperatures are possible with an implant energy of 1 MeV as a result of the lower total vacancy production in the near-surface region (despite the higher dose required to attain a comparable maximum 0 concentration of 67 atomic percent). These observations are attributable to the reduced rate of nuclear energy deposition in the near-surface region for 1 MeV 0 ions. As a consequence, a reduced defect density is potentially achievable with high-energy implantation and furthermore, the formation of buried SiO, layers at low implantation temperatures (15O’C) can be investigated. For GaAs and InP devices, device/substrate electrical isolation is achieved through device fabrication in conductive surface layers deposited epitaxially on semi-insulating substrates. Device/ device parasitic effects are minimized by rendering conductive material

0 1994 - Elsevier Science B.V. All rights reserved

SSDI 0168-583X(94)00032-Q

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Fig. 1. Theoretical vacancy distributions for 0.2 (dotted line) and 1.0 MeV (solid line) O-ion implantation in Si to doses of 1.45x 1018 and 2.15x 10’8/cm2, respectively. From ref. [3].

between devices semi-insulating through ion implantation [2] or alternatively, removing the conductive material through mesa etching. Implant isolation is advantageous in that surface planarity is maintained and, in general, less intrusion under the mask edges is observed [2]. With this methodology, compensation is achieved by the introduction of either damage- or chemically-related deep levels which trap free carriers. (Such traps are not thermally-ionized at device operating temperatures.) With the former, vertical devices of thickness l-2 pm (such as heterojunction bipolar transistors) typically require multiple low-energy (< 200 keV), multiple iight-ion (H, He, B, 0 or F) implantation to produce the disorder distribution required for

electrical isolation over the extent of the device. Postimplantation annealing at a temperature of * 500°C is necessary to minimize hopping conduction and thermally stabilize implantation-induced disorder [2]. Theoretical vacancy distributions are shown in Fig. 2 for both multiple-energy (0.1, 0.5 and 1.0 MeV) and single, high-energy (5.0 MeV) O-ion implant schemes in InP. With the latter, the rate of nuclear energy deposition (and hence, disorder production) in the near-surface region is reduced and also, is essentially constant. Thus, high-energy implantation can effectively reduce the number of implantation steps required for electrical isolation of a vertical device. Though the ion dose is necessarily increased to produce comparable total disorder over the extent of the conductive layer, the end-of-range disorder associated with high-energy implantation is confined to depths several times that of the active region. From the preceeding description of group IV and III-V implant isolation schemes, the necessity of both materials- and device-specific processing is apparent. For example, an implant isolation scheme based on the production of mid-gap carrier traps is inapplicable to Si given the lack of suitable implantation-induced deep levels in this material. Similarily, this scheme is inappropriate for III-V materials of significantly lesser band-gap (InGaAs, for example), for given complete compensation of the extrinsic carriers, the thermallygenerated intrinsic carrier concentration is still sufficient to limit the achievable resistivity to levels inadequate for electrical isolation. Conversely, an implant isolation scheme based on the fabrication of a buried oxide layer is inapplicable for III-V devices given the inability to produce a quality, stable oxide in such materials.

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MODIFICATION

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2. Experimental

Though details of the processing are given in refs. [3-51 and [6-91 for group IV and III-V high-energy implant isolation schemes, respectively, the experimental procedures are briefly described herein. For Si, substrates of (100) orientation were implanted at temperatures of HO-450°C with l.O-MeV 0 ions to doses of 2.18 x 101s/cm2. Selected samples were subsequently implanted with Si ions at a variety of temperatures (75-3OO”C), doses (1 x 10i5-1 x lO”/cm*l and energies (0.1-4.2 MeV). Post-implantation annealing was performed at temperatures of 1250-1300°C in an Ar/O (98%/2%) ambient for 2 h. Prior to annealing, selected samples were capped with 0.5 urn of SiO, deposited by plasma-enhanced chemical vapour deposition. Rutherford backscattering spectrometry combined with channeling (RBS/C) and cross-sectional transmission electron microscopy (XTEM) were utilized for characterization. For the III-V materials, either doped epitaxial layers or test structures on semi-insulating substrates of (100) orientation were implanted at room temperature with 0 ions to a variety of doses (1 X 10”-1 X 1015/cm2) and energies 0.1-5.0 MeV. Samples were annealed in an Ar ambient for 10 min at temperatures of 150-700°C. Sheet resistance measurements were performed with alloyed contacts in the Van der Pauw geometry.

3. Results and discussion 3.1. High-energy implant isolation in Si: Fig. 3 shows RBS/C planted at a temperature

spectra of Si substrates imof 150°C with I-MeV 0 ions

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[3]. For the as-implanted sample (Fig. 3a), three distinct regions of disorder are apparent - a damaged surface layer (channels 290-3301, an intermediate layer (channels 240-290) with a high rate of dechanneling (due to dislocations, as identified from XTEM analysis) and an amorphous layer (channels 130-240) centred approximately at the nuclear-energy deposition maximum. A comparable dose implanted at an energy of 200 keV would result in amorphization to the substrate surface and hence, polycrystalline formation over the extent of the Si overlayer upon annealing. For the annealed sample (Fig. 3b), the formation of a buried SiO, layer (channels 140-200) is readily apparent. During high-temperature annealing, thermodynamical considerations govern the formation of this layer via Ostwald ripening: SiO, precipitates below a temperature-dependent, critical radius r, dissolve whereas SiO, precipitates above rc grow from the dissolved 0. At very high temperatures, rc is such that only the buried SiO, layer is stable against dissolution. As apparent from Fig. 3b, a layer composed of polycrystalline Si (channels 205-235) and SiO, precipitates (channel 225) borders the front Si/SiO, interface. A thin region of microtwins (as identified from XTEM analysis) separates the polycrystalline layer from the crystalline Si over-layer. Competition between the two mechanisms for recrystallization of amorphous Si - solid phase epitaxy (SPE) and random nucleation and growth (RNG) - account for the formation of this disordered region. The dominant mechanism is a function of both temperature (SPE and RNG have activation energies of 2.7 and 3.4-4.0 eV, respectively [lo]) and impurity concentration (0 retards the SPE rate [ll] yet enhances the RNG rate [lo]). During annealing, recrystallization of amorphous material can proEnergy

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M. C. Ridgway et al. / Nucl. Instr. and Meth. in Phys. Res. B 89 (I 994) 290-297

teed via SPE at temperatures of u 600°C. As the 0 concentration at the amorphous/ crystalline (a/c) interface increases, SPE is inhibited with a probable loss of interface planarity and subsequent twin formation. At higher temperatures, O-rich amorphous Si between the twinned region and buried SiO, layer can recrystallize via RNG. The dominance of one recrystallization process would be reflected in the nature of the disorder bordering the front Si/SiO, interface. Optimization of processing variables such as implantation dose,

Fig. 4. Post-anneal (125oOC/2 h) XTEM images for 1.0 MeV O-ion implantation in Si at temperatures of 150, 300 and 450°C and to a dose of 2.18 X 10’8/cm2. From ref. [3].

293

energy and temperature and the high-temperature annealing cycle could thus, alter the balance between SPE and RNG and hence, alter post-anneal disorder. (For example, prior to high-temperature annealing, prolonged low-temperature ( _ 600°C) annealing may enhance the extent of SPE). SPE and possibly RNG are complete prior to the onset of significant Ostwald ripening (1150-1200°C) and hence, the local O-rich environment potentially influences both recrystallization mechanisms. However, once the disordered layer has been depleted of 0 by high-temperature annealing, disorder at the front Si/SiO, interface can be reduced significantly with a post-anneal Si implant to amorphize the twinned and polycrystalline regions. During subsequent annealing, amorphous material, now denuded of 0, recrystallizes via SPE and thus, the twinned and polycrystalline material is eliminated [12]. XTEM images of annealed samples are shown in Fig. 4 as a function of implantation temperature. In general, the concentration of Si and SiO, precipitates in the buried SiO, and Si over-layer, respectively, increases with increasing implantation temperature while the planarity of the Si/SiO, interface decreases. These two trends are attributable to the increase in implantation-induced disorder with decreasing implantation temperature - the uniformity of the buried SiO, layer increases as the number of implantation-induced nucleation sites available for SiO, precipitation increases. Though this demonstrates an advantage of low-temperature implantation, the formation of an amorphous layer due to the reduction in dynamic annealing results in polycrystalline Si formation upon high-temperature annealing as described previously. In Fig. 4, polycrystalline Si is not apparent in samples implanted at 300 and 450°C as such temperatures were sufficient to inhibit significant amorphization. A pre-anneal, secondary’ Si-ion implant, with projected range either less than or greater than that of a primary dopant-ion implant, has been shown by others [13,14] to reduce post-anneal, secondary-defect concentrations at the dopant-ion projected range. The reduction is attributed to the gettering of Si interstitials generated by the dopant-ion implant to disorder associated with the secondary-ion implant. A similar approach has been applied to SIMOX substrates [4,5], fabricated as described above, with the aim of modifying the nature and/or amount of post-anneal disorder at the Si/SiO, interfaces. Figs. 5 and 6 show pre- and post-anneal RBS/C spectra, respectively, of SIMOX substrates with and without a pre-anneal, low-energy (0.1 MeV) Si-ion implant. As expected, the only difference apparent in the spectra of as-implanted samples is the disorder peak in the near-surface region associated with the Si-ion implant. Conversely, post-anneal spectra show dramatic differences - the front Si/SiO, VIII. BEAM MODIFICATION

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5. RBS/C spectra for unannealed, 1.0 MeV O-ion implantation in Si at a temperature of 300°C and dose of 2.18~ 10’s/cm2 showing channeled (dotted line) and random (solid line) orientations (a) without and (b) with a secondary, 0.1 MeV %-ion implant at a temperature of 150°C and to a dose of 6.5 X 10t5/cm2. From ref. [5].

interface is far more abrupt and at this depth, a significant reduction in the number of Si (channel _ 120)

and SiO, (channel _ 150) precipitates in the SiO, and Si layers, respectively, is observed. Disorder associated with the secondary implant thus effectively getters Si interstitials from depths near the front Si/SiO, interface. (Such interstitials can arise not only from implantation but from the volume expansion associated with SiO, formation.) The magnitude of this effect should be put in context with the relative disorder production in the near-surface region for implants of 0.1 MeV, 6.5 x 1015 Si/cm2 at 150°C compared with 1.0 MeV, 2.18 x 10” O/cm2 at 300°C. TRIM calculations [15]

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show u 25 times greater athermal vacancy production in the near-surface region for the latter though the actual, net difference is expected to be less given the differences in implant temperature. However, it is the nature of the secondary disorder to which this gettering phenomena is potentially attributable. In Fig. 5, note the band of dechanneling centres at channels 250-260 (identified as dislocations from XTEM analysis) and the disorder-free (by RBS/C) near-surface layer at channels 260-285 prior to the secondary implant. (The latter may attest to the effectiveness of the surface as a defect sink.) After the secondary implant, a direct scatter peak indicative of displaced lattice

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M.C. Ridgwayet al./Nucl. Instr. and Meth. in Phys. Rex B 89 (1994) 290-297

atoms is observable, superimposed on the dechanneling contribution from the aforementioned dislocations. The high-energy, high-dose, high-dose-rate and hightemperature O-ion implant parameters promote extended defect formation during implantation in the over-layer region. These implant conditions are lessened during Si-ion implantation, the result of which is primary defect formation (or clusters thereof). As anticipated, the secondary implant had no apparent influence on the back Si/SiO, interface given the extremely low diffusivity of Si in SiO,. Similarily, a secondary Si-ion implant at an energy of 4.2 MeV, with a projected range several times that of the buried SiO, layer, did not have a significant influence on the nature of the disorder in the Si over-layer. However, an increase in the planarity of the back Si/SiO, interface was apparent. The doses for the 4.2- and O.l-MeV Si-ion implants were such that the vacancy production in the near-surface region was comparable. Note that the vacancy production for the former was essentially uniform over the extent of the Si over-layer whilst it was confined to the near-surface region for the latter. This demonstrates the requirement of localized gettering sites generated by a gradient in the implantationinduced disorder distribution. Given such conditions, a secondary, pre-anneal Si-ion implant can effectively modify the nature of post-anneal disorder.

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3.2. High-energy implant isolation in InP and GaAs 0

Figs. 7a and b show sheet resistance measurements as a function of annealing temperature for p+-InP, comparing, respectively, the high- and low-energy O-ion implant isolation schemes depicted in Fig. 2 [6]. The two schemes yield comparable maximum sheet resistance values. Prior to annealing, implanted samples typically exhibit a three orders of magnitude increase in sheet resistance compared to the as-grown value. With annealing at temperatures < - 400°C excess deep levels are removed, hopping conduction is reduced and consequently, an increase in sheet resistance is observed. Further annealing at temperatures of 400-500°C decreases the number of deep levels to a value less than that required for complete compensation and thus, a decrease in sheet resistance is apparent. Implantation-induced deep levels are removed with annealing at temperatures > u 600°C and the sheet resistance returns to the as-grown value. The two implant schemes exhibit slight differences in thermal stability - note the temperatures at which the sheet resistance drops toward the as-grown value ( _ 400 and _ 500°C for the high- and low-energy implant isolation schemes, respectively). This difference is attributed to implantation-induced conduction in the substrate as demonstrated in Fig. 7c for high-energy O-ion implantation in semi-insulating InP. (In

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Fig. 7. Sheet resistance values as a function of dose and annealing temperature for (a) a single, high-energy O-ion implant in pC-InP/semi-insulating InP with doses of (~1 1 X 1013, (@I 1 X 1014 and (m) 1 X 1015/cm2, (b) a multiple, low-energy O-ion implant sequence in p+-InP/semi-insulating InP with doses of (0) 6.4,7.7 and 16.1 x 101Z/cm2 and Cm) 2.1, 2.6 and 5.4X 1013/cm2 and (c) a single, high-energy O-ion implant in semi-insulating InP with doses of (A) 1 x 1013, (01 1 X 1014 and ( n ) 1 x 10”/cm2. From ref. [6]. VIII. BEAM MODIFICATION

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Figs. 7a and c, note the common temperature (N 400°C) for the precipitous drop in sheet resistance.) The temperature dependence of the sheet resistance measurements shown in Fig. 7c results from the different annealing rates for implantation-induced donor and acceptor levels [16,17]. The extent of substrate conduction inherent with a high-energy implant isolation scheme is materials-specific, being particularly apparent with InP. None the less, substrate conduction is not expected to degrade the performance of devices with vertical current flow (such as heterojunction bipolar transistors) [9] nor in structures formed on conductive substrates (such as ridge-waveguide lasers) [ 181. The single, high-energy O-ion implant scheme has been utilized in the fabrication of GaAs/AlGaAs heterojunction bipolar transistors [8,9]. Device performance comparable to that achieved with a ten-step, low-energy, light-ion implant isolation scheme was achieved. Though the processing simplification inherent with a single-implant isolation scheme is obvious, a further advantage is the flexibility to increase the subcollector or emitter cap layer thicknesses to reduce parasitic resistances [8]. In the preceeding paragraphs, the advantages of a single, high-energy O-ion implant isolation scheme were demonstrated. However, given the high-energy capability, implantation need not be restricted to light-ion species. For a given projected range, heavy ions have greater range straggle than light ions and can thus be utilized to reduce the number of required implants while confining disorder to the active layer. As a consequence, disorder-induced conduction in the substrate is eliminated. Furthermore, the thermal stability of implant isolation achieved with 0 or F ions exceeds

that of H [2] and thus, the use of heavy ions could be beneficial in increasing device lifetime and/or the permissible post-anneal thermal budget. Fig. 8 shows the theoretical vacancy distribution for 3.0 MeV In-ion implantation in InP [7]. Note the broad vacancy distribution with a uniformity comparable to that of a multiple, low-energy O-ion implant scheme. Similar post-anneal sheet resistance values were achieved for the two implant schemes though no significant differences in the thermal stability were apparent.

4. Conclusions High-energy implant isolation schemes for both group IV and III-V materials have been described. For Si, SIMOX substrates can be fabricated with highenergy, high-dose O-ion implantation at implant temperatures (150°C) that favour the formation of a continuous buried SiO, layer. For InP and GaAs, high-energy implantation results in comparable electrical isolation to that achieved with low-energy implant schemes yet yields significant process simplification and flexibility. Furthermore, the application of this technology to the fabrication of GaAs/AlGaAs heterojunction bipolar transistors has been sucessfully demonstrated. In general, high-energy implant isolation offers significant materials- and/or device-specific advantages and compatibility with conventional processing technologies. Such benefits warrant further study and application.

Acknowledgements

We thank collaborators C. Jagadish, N. Hauser, S.J. Pearton, M. Davies and P.J. Schultz for helpful discussions and the Australian Telecommunications and Electronics Research Board, Telecom Australia and the Bilateral Science and Technology Program of the Australian Department of Industry, Technology and Commerce for financial support.

References [ll J.-P. Colinge,

Depth

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Fig. 8. Theoretical vacancy distributions in InP for (a) 0.1, 0.4 and 1.0 MeV O-ion implantation to doses of 2.1, 2.6 and 5.4 X 10’3/cm2, respectively (dotted line) and 3.0 MeV In-ion implantation to a dose of 4.8X 10’*/cm2 (solid line). From ref. [7].

Silicon-on-Insulator Technology: Materials to VLSI &luwer, Boston, 1991) and references therein. El S.J. Pearton, Mater. Sci. Rep. 4 (1990) 313, and references therein. 131 S.L. Ellingboe, M.C. Ridgway and P.J. Schultz, J. Appl. Phys. 73 (1993) 1133. [41 S.L. Ellingboe and M.C. Ridgway, in: Beam-Solid Interactions: Fundamentals and Applications, eds. M.A. Natasi, N. Herbots, L.R. Harriot and R.S. Averback (Mater. Res. Sot., Pittsburgh, PA, 1993) p. 147. [51 S.L. Ellingboe and M.C. Ridgway, J. Appl. Phys. to appear May 1994.

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[7] [8]

[9] [lo] [ll] [12] [13]

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VIII. BEAM MODIFICATION